src/mainboard/google/brya/variants/pirrha/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <gpio.h>
   6 #include <soc/romstage.h>
   7 #include <boardid.h>
   8
   9 static const struct mb_cfg variant_memcfg = {
  10         .type = MEM_TYPE_LP5X,
  11
  12         .rcomp = {
  13                 /* Baseboard uses only 100ohm Rcomp resistors */
  14                 .resistor = 100,
  15         },
  16
  17         /* DQ byte map */
  18         .lpx_dq_map = {
  19                 .ddr0 = {
  20                         .dq0 = { 15, 10,  8, 11, 14, 13,  9, 12 },
  21                         .dq1 = {  3,  1,  2,  0,  7,  5,  4,  6 },
  22                 },
  23                 .ddr1 = {
  24                         .dq0 = {  7,  0,  3,  2,  1,  4,  6,  5 },
  25                         .dq1 = { 12,  9,  8, 11, 10, 13, 15, 14 },
  26                 },
  27                 .ddr2 = {
  28                         .dq0 = {  2,  1,  3,  0,  4,  6,  5,  7 },
  29                         .dq1 = {  8,  9, 10, 11, 13, 14, 12, 15 },
  30                 },
  31                 .ddr3 = {
  32                         .dq0 = {  3,  0,  1,  2,  5,  6,  4,  7 },
  33                         .dq1 = { 13,  9, 11,  8, 14, 15, 10, 12 },
  34                 },
  35                 .ddr4 = {
  36                         .dq0 = { 15, 10,  8, 11, 14, 13,  9, 12 },
  37                         .dq1 = {  3,  1,  2,  0,  7,  5,  4,  6 },
  38                 },
  39                 .ddr5 = {
  40                         .dq0 = {  7,  0,  3,  2,  1,  4,  6,  5 },
  41                         .dq1 = { 12,  9,  8, 11, 10, 13, 15, 14 },
  42                 },
  43                 .ddr6 = {
  44                         .dq0 = {  2,  1,  3,  0,  4,  6,  5,  7 },
  45                         .dq1 = {  8,  9, 10, 11, 13, 14, 12, 15 },
  46                 },
  47                 .ddr7 = {
  48                         .dq0 = {  3,  0,  1,  2,  5,  6,  4,  7 },
  49                         .dq1 = { 13,  9, 11,  8, 14, 15, 10, 12 },
  50                 },
  51         },
  52
  53         /* DQS CPU<>DRAM map */
  54         .lpx_dqs_map = {
  55                 .ddr0 = { .dqs0 = 1, .dqs1 = 0 },
  56                 .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
  57                 .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
  58                 .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
  59                 .ddr4 = { .dqs0 = 1, .dqs1 = 0 },
  60                 .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
  61                 .ddr6 = { .dqs0 = 0, .dqs1 = 1 },
  62                 .ddr7 = { .dqs0 = 0, .dqs1 = 1 },
  63         },
  64
  65         .lp5x_config = {
  66                 .ccc_config = 0xff,
  67         },
  68
  69         .ect = 1, /* Early Command Training */
  70
  71         .UserBd = BOARD_TYPE_MOBILE,
  72 };
  73
  74 const struct mb_cfg *variant_memory_params(void)
  75 {
  76         return &variant_memcfg;
  77 }
  78
  79 int variant_memory_sku(void)
  80 {
  81         /*
  82          * Memory configuration board straps
  83          * GPIO_MEM_CONFIG_0    GPP_E1
  84          * GPIO_MEM_CONFIG_1    GPP_E2
  85          * GPIO_MEM_CONFIG_2    GPP_E3
  86          */
  87         gpio_t spd_gpios[] = {
  88                 GPP_E1,
  89                 GPP_E2,
  90                 GPP_E3,
  91         };
  92
  93         if (board_id() == BOARD_ID_UNKNOWN)
  94                 return 0;
  95
  96         return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
  97 }