src/mainboard/google/brya/variants/redrix4es/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A17 : DISP_MISCC ==> NC */
  11         PAD_NC(GPP_A17, NONE),
  12         /* A19 : DDSP_HPD1 ==> NC */
  13         PAD_NC(GPP_A19, NONE),
  14         /* A20 : DDSP_HPD2 ==> NC */
  15         PAD_NC(GPP_A20, NONE),
  16         /* A21 : DDPC_CTRCLK ==> NC */
  17         PAD_NC(GPP_A21, NONE),
  18         /* A22 : DDPC_CTRLDATA ==> NC */
  19         PAD_NC(GPP_A22, NONE),
  20
  21         /* B3  : PROC_GP2 ==> NC */
  22         PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
  23         /* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
  24         PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
  25         /* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
  26         PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
  27         /* B15  : TIME_SYNC0 ==> NC */
  28         PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
  29
  30         /* C3 : SML0CLK ==> NC */
  31         PAD_NC(GPP_C3, NONE),
  32         /* C4 : SML0DATA ==> NC */
  33         PAD_NC(GPP_C4, NONE),
  34
  35         /* D7  : SRCCLKREQ2# ==> NC */
  36         PAD_NC(GPP_D7, NONE),
  37         /* D13 : ISH_UART0_RXD ==> NC */
  38         PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
  39
  40         /* E3  : PROC_GP0 ==> NC */
  41         PAD_NC(GPP_E3, NONE),
  42         /* E7  : PROC_GP1 ==> NC */
  43         PAD_NC(GPP_E7, NONE),
  44         /* E16 : RSVD_TP ==> WWAN_RST_L */
  45         PAD_CFG_GPO(GPP_E16, 1, DEEP),
  46         /* E20 : DDP2_CTRLCLK ==> NC */
  47         PAD_NC(GPP_E20, NONE),
  48         /* E22 : DDPA_CTRLCLK ==> NC */
  49         PAD_NC(GPP_E22, NONE),
  50         /* E23 : DDPA_CTRLDATA ==> NC */
  51         PAD_NC(GPP_E23, NONE),
  52         /* F20 : EXT_PWR_GATE# ==> NC */
  53         PAD_NC(GPP_F20, NONE),
  54
  55         /* H3  : SX_EXIT_HOLDOFF# ==> NC */
  56         PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG),
  57         /* H20 : IMGCLKOUT1 ==> NC */
  58         PAD_NC(GPP_H20, NONE),
  59         /* H21 : IMGCLKOUT2 ==> Privacy screen */
  60         PAD_CFG_GPO(GPP_H21, 0, DEEP),
  61
  62         /* R6 : I2S_PCH_TX_SPKR_RX ==> NC */
  63         PAD_NC(GPP_R6, NONE),
  64         /* R7 : I2S_PCH_RX_SPKR_TX ==> NC */
  65         PAD_NC(GPP_R7, NONE),
  66
  67         /* S4 : SNDW2_CLK ==> NC */
  68         PAD_NC(GPP_S4, NONE),
  69         /* S5 : SNDW2_DATA ==> NC */
  70         PAD_NC(GPP_S5, NONE),
  71         /* S6 : SNDW3_CLK ==> NC */
  72         PAD_NC(GPP_S6, NONE),
  73         /* S7 : SNDW3_DATA ==> NC */
  74         PAD_NC(GPP_S7, NONE),
  75         /*
  76          * E0 : SATAXPCIE0 ==> WWAN_PERST_L
  77          * Drive high here, so that PERST_L is sequenced after RST_L
  78          */
  79         PAD_CFG_GPO(GPP_E0, 1, DEEP),
  80 };
  81
  82 /* Early pad configuration in bootblock */
  83 static const struct pad_config early_gpio_table[] = {
  84         /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
  85         PAD_CFG_GPO(GPP_A12, 1, DEEP),
  86         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
  87         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
  88         /* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
  89         PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
  90         /* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
  91         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
  92         /*
  93          * D1  : ISH_GP1 ==> FP_RST_ODL
  94          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
  95          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
  96          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
  97          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
  98          * FPMCU not working after a S3 resume. This is a known issue.
  99          */
 100         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 101         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 102         PAD_CFG_GPO(GPP_D2, 1, DEEP),
 103         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
 104         PAD_CFG_GPO(GPP_D11, 1, DEEP),
 105         /* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
 106         PAD_CFG_GPO(GPP_E0, 0, DEEP),
 107         /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
 108         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 109         /* E15 : RSVD_TP ==> PCH_WP_OD */
 110         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 111         /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
 112         PAD_CFG_GPO(GPP_E16, 0, DEEP),
 113         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 114         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 115         /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
 116         PAD_CFG_GPO(GPP_F21, 0, DEEP),
 117         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 118         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 119         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 120         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 121         /*
 122          * enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and
 123          * then deassert PERST# in romstage
 124          */
 125         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 126         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 127         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 128         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 129 };
 130
 131 static const struct pad_config romstage_gpio_table[] = {
 132         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 133         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 134
 135         /* Enable touchscreen, hold in reset */
 136         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
 137         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 138         /* C1  : SMBDATA ==> USI_RST_L */
 139         PAD_CFG_GPO(GPP_C1, 0, DEEP),
 140
 141         /* D1  : ISH_GP1 ==> FP_RST_ODL */
 142         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 143         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 144         PAD_CFG_GPO(GPP_D2, 0, DEEP),
 145
 146         /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
 147         PAD_CFG_GPO(GPP_F21, 1, DEEP),
 148 };
 149
 150 const struct pad_config *variant_gpio_override_table(size_t *num)
 151 {
 152         *num = ARRAY_SIZE(override_gpio_table);
 153         return override_gpio_table;
 154 }
 155
 156 const struct pad_config *variant_early_gpio_table(size_t *num)
 157 {
 158         *num = ARRAY_SIZE(early_gpio_table);
 159         return early_gpio_table;
 160 }
 161
 162 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 163 {
 164         *num = ARRAY_SIZE(romstage_gpio_table);
 165         return romstage_gpio_table;
 166 }