?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mb/lenovo/x230: Remove old USB configurations
[coreboot2.git] / src / mainboard / google / brya / variants / rull / overridetree.cb
blob6e7c2c229a36d0061ff91e19f7f77f3be7fc5ebf
1 fw_config
2 field THERMAL 18 18
3 option THERMAL_6W 0
4 option THERMAL_15W 1
5 end
6 field WIFI 8 9
7 option WIFI_CNVI_WIFI6E 0
8 option WIFI_PCIE_WIFI7 1
9 option WIFI_UNKNOWN 2
10 end
11
12 end
13
14 chip soc/intel/alderlake
15 # Acoustic settings
16 register "acoustic_noise_mitigation" = "true"
17 register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_4"
18 register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_4"
19 register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "true"
20 register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "true"
21
22 register "sagv" = "SaGv_Enabled"
23
24 # EMMC Tx CMD Delay
25 # Refer to EDS-Vol2-42.3.7.
26 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
27 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
28 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
29
30 # EMMC TX DATA Delay 1
31 # Refer to EDS-Vol2-42.3.8.
32 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
33 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
34 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
35
36 # EMMC TX DATA Delay 2
37 # Refer to EDS-Vol2-42.3.9.
38 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
39 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
40 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
41 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
42 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
43
44 # EMMC RX CMD/DATA Delay 1
45 # Refer to EDS-Vol2-42.3.10.
46 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
47 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
48 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
49 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
50 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
51
52 # EMMC RX CMD/DATA Delay 2
53 # Refer to EDS-Vol2-42.3.12.
54 # [17:16] stands for Rx Clock before Output Buffer,
55 # 00: Rx clock after output buffer,
56 # 01: Rx clock before output buffer,
57 # 10: Automatic selection based on working mode.
58 # 11: Reserved
59 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
60 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
61 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004C"
62
63 # EMMC Rx Strobe Delay
64 # Refer to EDS-Vol2-42.3.11.
65 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
66 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
67 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
68
69 # SOC Aux orientation override:
70 # This is a bitfield that corresponds to up to 4 TCSS ports.
71 # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
72 # TcssAuxOri = 0100b
73 # Bit0 set to "0" indicates has retimer on USBC Port0, on the DB.
74 # Bit2 set to "1" indicates no retimer on USBC Port1, on the MB.
75 # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
76 # motherboard to USBC connector
77 register "tcss_aux_ori" = "5"
78
79 register "typec_aux_bias_pads[0]" = "{
80 .pad_auxp_dc = GPP_A19,
81 .pad_auxn_dc = GPP_A20
82 }"
83
84 register "typec_aux_bias_pads[1]" = "{
85 .pad_auxp_dc = GPP_E22,
86 .pad_auxn_dc = GPP_E23
87 }"
88
89 # FIVR configurations for rull are disabled since the board doesn't have V1p05 and Vnn
90 # bypass rails implemented.
91 register "ext_fivr_settings" = "{
92 .configure_ext_fivr = 0,
93 }"
94
95 # Enable the Cnvi BT Audio Offload
96 register "cnvi_bt_audio_offload" = "1"
97
98 # Intel Common SoC Config
99 #+-------------+------------------------------+
100 #| Field | Value |
101 #+-------------+------------------------------+
102 #| I2C0 | TPM. Early init is |
103 #| | required to set up a BAR |
104 #| | for TPM communication |
105 #| I2C1 | Touchscreen |
106 #| I2C3 | Audio |
107 #| I2C5 | Trackpad |
108 #+-------------+------------------------------+
109 register "common_soc_config" = "{
110 .i2c[0] = {
111 .early_init = 1,
112 .speed = I2C_SPEED_FAST_PLUS,
113 .speed_config[0] = {
114 .speed = I2C_SPEED_FAST_PLUS,
115 .scl_lcnt = 55,
116 .scl_hcnt = 30,
117 .sda_hold = 7,
118 }
119 },
120 .i2c[1] = {
121 .speed = I2C_SPEED_FAST,
122 .speed_config[0] = {
123 .speed = I2C_SPEED_FAST,
124 .scl_lcnt = 160,
125 .scl_hcnt = 79,
126 .sda_hold = 7,
127 }
128 },
129 .i2c[3] = {
130 .speed = I2C_SPEED_FAST,
131 .speed_config[0] = {
132 .speed = I2C_SPEED_FAST,
133 .scl_lcnt = 157,
134 .scl_hcnt = 79,
135 .sda_hold = 7,
136 }
137 },
138 .i2c[5] = {
139 .speed = I2C_SPEED_FAST,
140 .speed_config[0] = {
141 .speed = I2C_SPEED_FAST,
142 .scl_lcnt = 152,
143 .scl_hcnt = 79,
144 .sda_hold = 7,
145 }
146 },
147 }"
148
149 # Power limit config
150 register "power_limits_config[ADL_N_041_6W_CORE]" = "{
151 .tdp_pl1_override = 15,
152 .tdp_pl2_override = 25,
153 .tdp_pl4 = 78,
154 }"
155 register "power_limits_config[ADL_N_081_15W_CORE]" = "{
156 .tdp_pl1_override = 22,
157 .tdp_pl2_override = 35,
158 .tdp_pl4 = 83,
159 }"
160 device domain 0 on
161 device ref dtt on
162 chip drivers/intel/dptf
163 ## sensor information
164 register "options.tsr[0].desc" = ""CPU_VR""
165 register "options.tsr[1].desc" = ""CPU""
166 register "options.tsr[2].desc" = ""Ambient""
167 register "options.tsr[3].desc" = ""Charger""
168
169 # TODO: below values are initial reference values only
170 ## Passive Policy
171 register "policies.passive" = "{
172 [0] = DPTF_PASSIVE(CPU, CPU, 85, 4000),
173 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 4000),
174 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 4000),
175 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 4000),
176 [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 4000),
177 }"
178
179 ## Critical Policy
180 register "policies.critical" = "{
181 [0] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN),
182 [1] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN),
183 }"
184
185 register "controls.power_limits" = "{
186 .pl1 = {
187 .min_power = 6000,
188 .max_power = 13000,
189 .time_window_min = 28 * MSECS_PER_SEC,
190 .time_window_max = 32 * MSECS_PER_SEC,
191 .granularity = 200
192 },
193 .pl2 = {
194 .min_power = 25000,
195 .max_power = 25000,
196 .time_window_min = 28 * MSECS_PER_SEC,
197 .time_window_max = 32 * MSECS_PER_SEC,
198 .granularity = 1000
199 }
200 }"
201
202 ## Charger Performance Control (Control, mA)
203 register "controls.charger_perf" = "{
204 [0] = { 255, 4700 },
205 [1] = { 40, 2500 },
206 [2] = { 16, 1000 },
207 [3] = { 8, 500 }
208 }"
209
210 device generic 0 on
211 probe THERMAL THERMAL_6W
212 end
213 end
214
215 chip drivers/intel/dptf
216 ## sensor information
217 register "options.tsr[0].desc" = ""CPU_VR""
218 register "options.tsr[1].desc" = ""CPU""
219 register "options.tsr[2].desc" = ""Ambient""
220 register "options.tsr[3].desc" = ""Charger""
221
222 # TODO: below values are initial reference values only
223 ## Active Policy
224 register "policies.active" = "{
225 [0] = {
226 .target = DPTF_TEMP_SENSOR_0,
227 .thresholds = {
228 TEMP_PCT(85, 90),
229 TEMP_PCT(44, 61),
230 TEMP_PCT(42, 54),
231 TEMP_PCT(40, 45),
232 TEMP_PCT(38, 38),
233 TEMP_PCT(36, 25),
234 }
235 },
236 [1] = {
237 .target = DPTF_TEMP_SENSOR_1,
238 .thresholds = {
239 TEMP_PCT(75, 90),
240 TEMP_PCT(70, 80),
241 TEMP_PCT(65, 70),
242 TEMP_PCT(60, 60),
243 TEMP_PCT(55, 50),
244 TEMP_PCT(50, 40),
245 }
246 },
247 [2] = {
248 .target = DPTF_TEMP_SENSOR_2,
249 .thresholds = {
250 TEMP_PCT(90, 90),
251 TEMP_PCT(85, 80),
252 TEMP_PCT(75, 70),
253 TEMP_PCT(70, 50),
254 }
255 },
256 [3] = {
257 .target = DPTF_TEMP_SENSOR_3,
258 .thresholds = {
259 TEMP_PCT(80, 90),
260 TEMP_PCT(75, 80),
261 TEMP_PCT(70, 70),
262 TEMP_PCT(65, 50),
263 }
264 }
265 }"
266 ## Passive Policy
267 register "policies.passive" = "{
268 [0] = DPTF_PASSIVE(CPU, CPU, 85, 6000),
269 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 6000),
270 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 6000),
271 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 6000),
272 [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 6000),
273 }"
274
275 ## Critical Policy
276 register "policies.critical" = "{
277 [0] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN),
278 [1] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN),
279 }"
280
281 register "controls.power_limits" = "{
282 .pl1 = {
283 .min_power = 15000,
284 .max_power = 22000,
285 .time_window_min = 28 * MSECS_PER_SEC,
286 .time_window_max = 32 * MSECS_PER_SEC,
287 .granularity = 200
288 },
289 .pl2 = {
290 .min_power = 35000,
291 .max_power = 35000,
292 .time_window_min = 28 * MSECS_PER_SEC,
293 .time_window_max = 32 * MSECS_PER_SEC,
294 .granularity = 1000
295 }
296 }"
297
298 ## Charger Performance Control (Control, mA)
299 register "controls.charger_perf" = "{
300 [0] = { 255, 4700 },
301 [1] = { 40, 2500 },
302 [2] = { 16, 1000 },
303 [3] = { 8, 500 }
304 }"
305
306 ## Fan Performance Control (Percent, Speed, Noise, Power)
307 register "controls.fan_perf" = "{
308 [0] = { 100, 4400, 220, 1640, },
309 [1] = { 90, 4100, 220, 1640, },
310 [2] = { 80, 3800, 180, 1310, },
311 [3] = { 70, 3500, 145, 1030, },
312 [4] = { 60, 3100, 115, 765, },
313 [5] = { 50, 2800, 90, 545, },
314 [6] = { 40, 2400, 55, 365, },
315 [7] = { 30, 1900, 30, 220, },
316 [8] = { 20, 1400, 15, 120, },
317 [9] = { 0, 0, 0, 50, }
318 }"
319
320 ## Fan options
321 register "options.fan.fine_grained_control" = "true"
322 register "options.fan.step_size" = "2"
323 device generic 1 on
324 probe THERMAL THERMAL_15W
325 end
326 end
327 end
328
329 device ref igpu on
330 chip drivers/gfx/generic
331 register "device_count" = "4"
332 # DDIA for eDP
333 register "device[0].name" = ""LCD0""
334 # Internal panel on the first port of the graphics chip
335 register "device[0].type" = "panel"
336 # DDIB for HDMI
337 # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
338 register "device[1].name" = ""DD01""
339 # TCP0 (DP-1) for port C0
340 register "device[2].name" = ""DD02""
341 register "device[2].use_pld" = "true"
342 register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
343 # TCP1 (DP-2) for port C1
344 register "device[3].name" = ""DD03""
345 register "device[3].use_pld" = "true"
346 register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
347 device generic 0 on end
348 end
349 end
350 device ref i2c1 on
351 chip drivers/i2c/hid
352 register "generic.hid" = ""ELAN9004""
353 register "generic.desc" = ""ELAN Touchscreen""
354 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
355 register "generic.detect" = "1"
356 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
357 register "generic.reset_delay_ms" = "20"
358 register "generic.reset_off_delay_ms" = "2"
359 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
360 register "generic.stop_delay_ms" = "150"
361 register "generic.stop_off_delay_ms" = "2"
362 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
363 register "generic.enable_delay_ms" = "1"
364 register "generic.has_power_resource" = "1"
365 register "hid_desc_reg_offset" = "0x01"
366 device i2c 10 on end
367 end
368 chip drivers/i2c/hid
369 register "generic.hid" = ""GTCH7503""
370 register "generic.desc" = ""G2 Touchscreen""
371 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
372 register "generic.detect" = "1"
373 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
374 register "generic.reset_delay_ms" = "10"
375 register "generic.reset_off_delay_ms" = "3"
376 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
377 register "generic.enable_delay_ms" = "12"
378 register "generic.has_power_resource" = "1"
379 register "hid_desc_reg_offset" = "0x01"
380 device i2c 40 on end
381 end
382 end
383 device ref i2c3 on
384 chip drivers/i2c/rt5645
385 register "hid" = ""10EC5650""
386 register "name" = ""RT58""
387 register "desc" = ""Realtek RT5650""
388 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
389 register "cbj_sleeve" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
390 register "jd_mode" = "2"
391 device i2c 1a on end
392 end
393 end
394 device ref i2c5 on
395 chip drivers/i2c/hid
396 register "generic.hid" = ""SYNA0000""
397 register "generic.cid" = ""ACPI0C50""
398 register "generic.desc" = ""Synaptics Touchpad""
399 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
400 register "generic.wake" = "GPE0_DW2_14"
401 register "generic.detect" = "1"
402 register "hid_desc_reg_offset" = "0x20"
403 device i2c 2c on end
404 end
405 chip drivers/i2c/hid
406 register "generic.hid" = ""PNP0C50""
407 register "generic.desc" = ""PIXART Touchpad""
408 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
409 register "generic.wake" = "GPE0_DW2_14"
410 register "generic.detect" = "1"
411 register "hid_desc_reg_offset" = "0x20"
412 device i2c 68 on end
413 end
414 end
415 device ref cnvi_wifi on
416 chip drivers/wifi/generic
417 register "wake" = "GPE0_PME_B0"
418 register "enable_cnvi_ddr_rfim" = "true"
419 register "add_acpi_dma_property" = "true"
420 device generic 0 on end
421 end
422 probe WIFI WIFI_CNVI_WIFI6E
423 probe WIFI WIFI_UNKNOWN
424 end
425 device ref pcie_rp4 on
426 # PCIe 4 WLAN
427 register "pch_pcie_rp[PCH_RP(4)]" = "{
428 .clk_src = 2,
429 .clk_req = 2,
430 .flags = PCIE_RP_LTR | PCIE_RP_AER,
431 }"
432 chip drivers/wifi/generic
433 register "wake" = "GPE0_DW1_03"
434 register "add_acpi_dma_property" = "true"
435 device pci 00.0 on end
436 end
437 chip soc/intel/common/block/pcie/rtd3
438 # # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN
439 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
440 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
441 register "srcclk_pin" = "2"
442 device generic 0 on end
443 end
444 probe WIFI WIFI_PCIE_WIFI7
445 probe WIFI WIFI_UNKNOWN
446 end
447 device ref pch_espi on
448 chip ec/google/chromeec
449 use conn0 as mux_conn[0]
450 use conn1 as mux_conn[1]
451 device pnp 0c09.0 on end
452 end
453 end
454 device ref pmc hidden
455 chip drivers/intel/pmc_mux
456 device generic 0 on
457 chip drivers/intel/pmc_mux/conn
458 use usb2_port1 as usb2_port
459 use tcss_usb3_port2 as usb3_port
460 device generic 0 alias conn0 on end
461 end
462 chip drivers/intel/pmc_mux/conn
463 use usb2_port2 as usb2_port
464 use tcss_usb3_port1 as usb3_port
465 device generic 1 alias conn1 on end
466 end
467 end
468 end
469 end
470 device ref tcss_xhci on
471 chip drivers/usb/acpi
472 device ref tcss_root_hub on
473 chip drivers/usb/acpi
474 register "desc" = ""USB3 Type-C Port C0 (MLB)""
475 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
476 register "use_custom_pld" = "true"
477 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
478 device ref tcss_usb3_port2 on end
479 end
480 chip drivers/usb/acpi
481 register "desc" = ""USB3 Type-C Port C1 (DB)""
482 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
483 register "use_custom_pld" = "true"
484 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
485 device ref tcss_usb3_port1 on end
486 end
487 end
488 end
489 end
490 device ref xhci on
491 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C MB (7.5 inch)
492 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C DB (7.1 inch)
493 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MB (6.4 inch)
494 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A DB (6.2 inch)
495 register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # LTE (3.3 inch)
496 register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch)
497 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch)
498 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
499
500 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB)
501 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A1(DB)
502 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN(LTE)
503 chip drivers/usb/acpi
504 device ref xhci_root_hub on
505 chip drivers/usb/acpi
506 register "desc" = ""USB2 Type-C Port C0 (MLB)""
507 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
508 register "use_custom_pld" = "true"
509 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
510 device ref usb2_port1 on end
511 end
512 chip drivers/usb/acpi
513 register "desc" = ""USB2 Type-C Port C1 (DB)""
514 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
515 register "use_custom_pld" = "true"
516 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
517 device ref usb2_port2 on end
518 end
519 chip drivers/usb/acpi
520 register "desc" = ""USB2 Type-A Port A0 (MLB)""
521 register "type" = "UPC_TYPE_A"
522 register "use_custom_pld" = "true"
523 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
524 device ref usb2_port3 on end
525 end
526 chip drivers/usb/acpi
527 register "desc" = ""USB2 Type-A Port A1 (DB)""
528 register "type" = "UPC_TYPE_A"
529 register "use_custom_pld" = "true"
530 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
531 device ref usb2_port4 on end
532 end
533 chip drivers/usb/acpi
534 register "desc" = ""USB2 LTE""
535 register "type" = "UPC_TYPE_INTERNAL"
536 device ref usb2_port5 on end
537 end
538 chip drivers/usb/acpi
539 register "desc" = ""USB2 UFC""
540 register "type" = "UPC_TYPE_INTERNAL"
541 device ref usb2_port6 on end
542 end
543 chip drivers/usb/acpi
544 register "desc" = ""PCIe Bluetooth""
545 register "type" = "UPC_TYPE_INTERNAL"
546 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
547 device ref usb2_port8 on
548 probe WIFI WIFI_PCIE_WIFI7
549 probe WIFI WIFI_UNKNOWN
550 end
551 end
552 chip drivers/usb/acpi
553 register "desc" = ""CNVi Bluetooth""
554 register "type" = "UPC_TYPE_INTERNAL"
555 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
556 device ref usb2_port10 on
557 probe WIFI WIFI_CNVI_WIFI6E
558 probe WIFI WIFI_UNKNOWN
559 end
560 end
561 chip drivers/usb/acpi
562 register "desc" = ""USB3 Type-A Port A0 (MLB)""
563 register "type" = "UPC_TYPE_USB3_A"
564 register "use_custom_pld" = "true"
565 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
566 device ref usb3_port1 on end
567 end
568 chip drivers/usb/acpi
569 register "desc" = ""USB3 Type-A Port A1 (DB)""
570 register "type" = "UPC_TYPE_USB3_A"
571 register "use_custom_pld" = "true"
572 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
573 device ref usb3_port2 on end
574 end
575 chip drivers/usb/acpi
576 register "desc" = ""USB3 WWAN""
577 register "type" = "UPC_TYPE_INTERNAL"
578 device ref usb3_port3 on end
579 end
580 chip drivers/usb/acpi
581 register "desc" = ""USB3 WLAN""
582 register "type" = "UPC_TYPE_INTERNAL"
583 device ref usb3_port4 on end
584 end
585 end
586 end
587 end
588 device ref pcie_rp7 off end # SDCard
589 device ref pcie_rp9 on
590 # Enable NVMe SSD PCIe 9-12 using clk 1
591 register "pch_pcie_rp[PCH_RP(9)]" = "{
592 .clk_src = 1,
593 .clk_req = 1,
594 .flags = PCIE_RP_LTR | PCIE_RP_AER,
595 .pcie_rp_aspm = ASPM_L1,
596 }"
597 chip soc/intel/common/block/pcie/rtd3
598 # enable_gpio is EN_PP3300_SSD
599 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
600 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
601 register "srcclk_pin" = "1"
602 device generic 0 on end
603 end
604 probe STORAGE STORAGE_NVME
605 probe STORAGE STORAGE_UNKNOWN
606 end
607 device ref emmc on
608 probe STORAGE STORAGE_EMMC
609 probe STORAGE STORAGE_UNKNOWN
610 end
611 device ref hda on
612 chip drivers/sof
613 register "spkr_tplg" = "rt5650_sp"
614 register "jack_tplg" = "rt5650_hp"
615 register "mic_tplg" = "_2ch_pdm0"
616 device generic 0 on end
617 end
618 end
619 end
620 end
coreboot repo mirror