src/mainboard/google/brya/variants/uldren/variant.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <console/console.h>
   6 #include <sar.h>
   7
   8 static const struct pad_config touchscreen_disable_pads[] = {
   9         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR_X */
  10         PAD_NC(GPP_C0, NONE),
  11         /* C1  : SMBDATA ==> TCHSCR_RST_L */
  12         PAD_NC(GPP_C1, NONE),
  13         /* C6  : SML1CLK ==> TCHSCR_REPORT_EN */
  14         PAD_NC(GPP_C6, NONE),
  15         /* C7  : SML1DATA ==> TCHSCR_INT_ODL */
  16         PAD_NC(GPP_C7, NONE),
  17         /* H6  : I2C1_SDA ==> SOC_I2C_TCHSCR_SDA */
  18         PAD_NC(GPP_H6, NONE),
  19         /* H7  : I2C1_SCL ==> SOC_I2C_TCHSCR_SCL */
  20         PAD_NC(GPP_H7, NONE),
  21 };
  22
  23 static const struct pad_config lte_disable_pads[] = {
  24         /* A8  : WWAN_RF_DISABLE_ODL */
  25         PAD_NC(GPP_A8, NONE),
  26         /* D6  : SRCCLKREQ1# ==> WWAN_EN */
  27         PAD_NC(GPP_D6, NONE),
  28         /* F12 : WWAN_RST_L */
  29         PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
  30 };
  31
  32 const char *get_wifi_sar_cbfs_filename(void)
  33 {
  34         return "wifi_sar_0.hex";
  35 }
  36
  37 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
  38 {
  39         if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_NONE))) {
  40                 printk(BIOS_INFO, "Disable touchscreen GPIO pins.\n");
  41                 gpio_padbased_override(padbased_table, touchscreen_disable_pads,
  42                                                 ARRAY_SIZE(touchscreen_disable_pads));
  43         }
  44         if (fw_config_probe(FW_CONFIG(DB_LTE, LTE_ABSENT))) {
  45                 printk(BIOS_INFO, "Disable LTE GPIO pins.\n");
  46                 gpio_padbased_override(padbased_table, lte_disable_pads,
  47                                                 ARRAY_SIZE(lte_disable_pads));
  48         }
  49 }
  50
  51 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
  52 {
  53         if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_PRESENT))) {
  54                 config->ext_fivr_settings.configure_ext_fivr = 1;
  55                 config->ext_fivr_settings.v1p05_enable_bitmap =
  56                                 FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0;
  57                 config->ext_fivr_settings.vnn_enable_bitmap =
  58                                 FIVR_ENABLE_ALL_SX;
  59                 config->ext_fivr_settings.vnn_sx_enable_bitmap =
  60                                 FIVR_ENABLE_ALL_SX;
  61                 config->ext_fivr_settings.v1p05_supported_voltage_bitmap =
  62                                 FIVR_VOLTAGE_NORMAL;
  63                 config->ext_fivr_settings.vnn_supported_voltage_bitmap =
  64                                 FIVR_VOLTAGE_MIN_ACTIVE;
  65                 config->ext_fivr_settings.v1p05_voltage_mv = 1050;
  66                 config->ext_fivr_settings.vnn_voltage_mv = 780;
  67                 config->ext_fivr_settings.vnn_sx_voltage_mv = 1050;
  68                 config->ext_fivr_settings.v1p05_icc_max_ma = 500;
  69                 config->ext_fivr_settings.vnn_icc_max_ma = 500;
  70                 printk(BIOS_INFO, "Configured External FIVR\n");
  71         }
  72 }