src/mainboard/google/brya/variants/volmar/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A6  : ESPI_ALERT1# ==> NC */
  11         PAD_NC(GPP_A6, NONE),
  12         /* A7  : SRCCLK_OE7# ==> NC */
  13         PAD_NC(GPP_A7, NONE),
  14         /* A8  : SRCCLKREQ7# ==> NC */
  15         PAD_NC(GPP_A8, NONE),
  16         /* A12 : SATAXPCIE1 ==>  NC  */
  17         PAD_NC(GPP_A12, NONE),
  18         /* A15 : USB_OC2# ==> NC */
  19         PAD_NC(GPP_A15, NONE),
  20         /* A19 : DDSP_HPD1 ==> NC */
  21         PAD_NC(GPP_A19, NONE),
  22         /* A20 : DDSP_HPD2 ==> NC */
  23         PAD_NC(GPP_A20, NONE),
  24         /* A21 : DDPC_CTRCLK ==> NC */
  25         PAD_NC(GPP_A21, NONE),
  26         /* A22 : DDPC_CTRLDATA ==> NC */
  27         PAD_NC(GPP_A22, NONE),
  28
  29         /* B3  : PROC_GP2 ==> NC */
  30         PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
  31
  32         /* D3  : ISH_GP3 ==> NC */
  33         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  34         /* D5  : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
  35         PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
  36         /* D6  : SRCCLKREQ1# ==> APU_PEN_DETECT_ODL */
  37         PAD_CFG_GPI_GPIO_DRIVER(GPP_D6, NONE, PLTRST),
  38         /* D7  : SRCCLKREQ2# ==> NC */
  39         PAD_NC(GPP_D7, NONE),
  40         /* D8  : SRCCLKREQ3# ==> NC */
  41         PAD_NC(GPP_D8, NONE),
  42         /* D9  : ISH_SPI_CS# ==> NC */
  43         PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
  44         /* D16 : ISH_UART0_CTS# ==> NC */
  45         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  46         /* D17  : UART1_RXD ==> APU_PEN_DETECT_ODL */
  47         PAD_CFG_GPI_SCI_LOCK(GPP_D17, NONE, EDGE_SINGLE, NONE, LOCK_CONFIG),
  48         /* D18 : UART1_TXD ==> NC */
  49         PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG),
  50
  51         /* E0  : SATAXPCIE0 ==> NC */
  52         PAD_NC(GPP_E0, NONE),
  53         /* E3  : PROC_GP0 ==> NC */
  54         PAD_NC(GPP_E3, NONE),
  55         /* E4  : SATA_DEVSLP0 ==> NC */
  56         PAD_NC(GPP_E4, NONE),
  57         /* E7  : PROC_GP1 ==> NC */
  58         PAD_NC(GPP_E7, NONE),
  59         /* E10 : THC0_SPI1_CS# ==> NC */
  60         PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
  61         /* E17 : THC0_SPI1_INT# ==> NC */
  62         PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
  63         /* E18 : DDP1_CTRLCLK ==> NC */
  64         PAD_NC(GPP_E18, NONE),
  65         /* E20 : DDP2_CTRLCLK ==> NC */
  66         PAD_NC(GPP_E20, NONE),
  67
  68         /* F6  : CNV_PA_BLANKING ==> NC */
  69         PAD_NC(GPP_F6, NONE),
  70         /* F20 : EXT_PWR_GATE# ==> NC */
  71         PAD_NC(GPP_F20, NONE),
  72         /* F21 : EXT_PWR_GATE2# ==> NC */
  73         PAD_NC(GPP_F21, NONE),
  74
  75         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
  76         PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG),
  77         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
  78         PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG),
  79         /* H8  : I2C4_SDA ==> NC */
  80         PAD_NC(GPP_H8, NONE),
  81         /* H9  : I2C4_SCL ==> NC */
  82         PAD_NC(GPP_H9, NONE),
  83         /* H12 : I2C7_SDA ==> NC */
  84         PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
  85         /* H13 : I2C7_SCL ==> NC */
  86         PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
  87         /* H19 : SRCCLKREQ4# ==> EMMC_CLKREQ_ODL */
  88         PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
  89         /* H20 : IMGCLKOUT1 ==> NC */
  90         PAD_NC(GPP_H20, NONE),
  91         /* H21 : IMGCLKOUT2 ==> NC */
  92         PAD_NC(GPP_H21, NONE),
  93         /* H22 : IMGCLKOUT3 ==> NC */
  94         PAD_NC(GPP_H22, NONE),
  95         /* H23 : SRCCLKREQ5# ==> NC */
  96         PAD_NC(GPP_H23, NONE),
  97
  98         /* R4 : HDA_RST# ==> DMIC_CLK0_R */
  99         PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
 100         /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */
 101         PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
 102         /* R6 : I2S2_TXD ==> DMIC_CLK1_R */
 103         PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
 104         /* R7 : I2S2_RXD ==> DMIC_DATA1_R */
 105         PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
 106
 107         /* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */
 108         PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
 109         /* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */
 110         PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
 111         /* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */
 112         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
 113         /* S3 : SNDW1_DATA ==> I2S1_PCH_RX_SPKR_TX */
 114         PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
 115
 116         /* GPD11: LANPHYC ==> NC */
 117         PAD_NC(GPD11, NONE),
 118 };
 119
 120 /* Early pad configuration in bootblock */
 121 static const struct pad_config early_gpio_table[] = {
 122         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 123         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 124         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 125         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 126         /*
 127          * D1  : ISH_GP1 ==> FP_RST_ODL
 128          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
 129          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
 130          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
 131          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
 132          * FPMCU not working after a S3 resume. This is a known issue.
 133          */
 134         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 135         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 136         PAD_CFG_GPO(GPP_D2, 1, DEEP),
 137         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
 138         PAD_CFG_GPO(GPP_D11, 1, DEEP),
 139         /* E0  : SATAXPCIE0 ==> NC */
 140         PAD_NC(GPP_E0, NONE),
 141         /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
 142         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 143         /* E15 : RSVD_TP ==> PCH_WP_OD */
 144         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 145         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 146         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 147         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 148         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 149         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 150         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 151         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 152         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 153         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 154         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 155
 156         /* CPU PCIe VGPIO for PEG60 */
 157         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
 158         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
 159         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
 160         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
 161         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
 162         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
 163         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
 164         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
 165         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
 166         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
 167         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
 168         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
 169         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
 170         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
 171         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
 172         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
 173         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
 174         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
 175         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
 176         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 177 };
 178
 179 static const struct pad_config romstage_gpio_table[] = {
 180         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 181         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 182
 183         /* Enable touchscreen, hold in reset */
 184         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
 185         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 186         /* C1  : SMBDATA ==> USI_RST_L */
 187         PAD_CFG_GPO(GPP_C1, 0, DEEP),
 188
 189         /* D1  : ISH_GP1 ==> FP_RST_ODL */
 190         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 191         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 192         PAD_CFG_GPO(GPP_D2, 0, DEEP),
 193 };
 194
 195 const struct pad_config *variant_gpio_override_table(size_t *num)
 196 {
 197         *num = ARRAY_SIZE(override_gpio_table);
 198         return override_gpio_table;
 199 }
 200
 201 const struct pad_config *variant_early_gpio_table(size_t *num)
 202 {
 203         *num = ARRAY_SIZE(early_gpio_table);
 204         return early_gpio_table;
 205 }
 206
 207 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 208 {
 209         *num = ARRAY_SIZE(romstage_gpio_table);
 210         return romstage_gpio_table;
 211 }