src/mainboard/google/brya/variants/xol/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/variants.h>
   4 #include <soc/romstage.h>
   5
   6 static const struct mb_cfg variant_memcfg = {
   7         .type = MEM_TYPE_LP5X,
   8
   9         .rcomp = {
  10                 /* Baseboard uses only 100ohm Rcomp resistors */
  11                 .resistor = 100,
  12         },
  13
  14         /* DQ byte map */
  15         .lpx_dq_map = {
  16                 .ddr0 = {
  17                         .dq0 = { 11, 10,  9,  8, 15, 14, 13, 12 },
  18                         .dq1 = {  7,  5,  4,  6,  1,  2,  0,  3 },
  19                 },
  20                 .ddr1 = {
  21                         .dq0 = {  1,  4,  0,  2,  5,  3,  6,  7 },
  22                         .dq1 = { 14, 13, 12, 15, 11, 10,  9,  8 },
  23                 },
  24                 .ddr2 = {
  25                         .dq0 = { 11, 10,  9,  8, 13, 15, 12, 14 },
  26                         .dq1 = {  4,  6,  7,  5,  0,  1,  2,  3 },
  27                 },
  28                 .ddr3 = {
  29                         .dq0 = {  4,  5,  1,  0,  7,  2,  6,  3 },
  30                         .dq1 = { 15, 11, 10, 14,  9,  8, 13, 12 },
  31                 },
  32                 .ddr4 = {
  33                         .dq0 = { 10,  9,  8, 11, 13, 15, 14, 12 },
  34                         .dq1 = {  5,  4,  3,  6,  2,  1,  0,  7 },
  35                 },
  36                 .ddr5 = {
  37                         .dq0 = {  0,  5,  1,  4,  6,  3,  7,  2 },
  38                         .dq1 = { 10, 11, 13, 15, 14,  9, 12,  8 },
  39                 },
  40                 .ddr6 = {
  41                         .dq0 = {  9, 10, 11,  8, 14, 12, 13, 15 },
  42                         .dq1 = {  5,  7,  6,  4,  1,  2,  3,  0 },
  43                 },
  44                 .ddr7 = {
  45                         .dq0 = {  3,  1,  2,  0,  7,  6,  5,  4 },
  46                         .dq1 = { 10,  9, 15, 13, 11, 12, 14,  8 },
  47                 },
  48         },
  49
  50         /* DQS CPU<>DRAM map */
  51         .lpx_dqs_map = {
  52                 .ddr0 = { .dqs0 = 1, .dqs1 = 0 },
  53                 .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
  54                 .ddr2 = { .dqs0 = 1, .dqs1 = 0 },
  55                 .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
  56                 .ddr4 = { .dqs0 = 1, .dqs1 = 0 },
  57                 .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
  58                 .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
  59                 .ddr7 = { .dqs0 = 0, .dqs1 = 1 },
  60         },
  61
  62         .lp5x_config = {
  63                 .ccc_config = 0xff,
  64         },
  65
  66         .LpDdrDqDqsReTraining = 1,
  67
  68         .ect = 1, /* Early Command Training */
  69
  70         .UserBd = BOARD_TYPE_ULT_ULX,
  71 };
  72
  73 const struct mb_cfg *variant_memory_params(void)
  74 {
  75         return &variant_memcfg;
  76 }