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soc/mediatek/common: Fix wrong write API for protect_key_setting
[coreboot2.git] / src / mainboard / google / brya / variants / xol / overridetree.cb
blob69209fa7311c01bf187db361e72b073516a3f7fd
1 fw_config
2 field STORAGE 0 0
3 option STORAGE_UFS 0
4 option STORAGE_NVME 1
5 end
6 field WIFI_SAR_ID 31
7 option WIFI_SAR_ID_0 0
8 option WIFI_SAR_ID_1 1
9 end
10 end
11
12 chip soc/intel/alderlake
13 register "domain_vr_config[VR_DOMAIN_IA]" = "{
14 .enable_fast_vmode = 1,
15 }"
16
17 # Acoustic settings
18 register "acoustic_noise_mitigation" = "true"
19 register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_4"
20 register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_4"
21 register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
22 register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
23
24 register "sagv" = "SaGv_Enabled"
25
26 # As per Intel Advisory doc#723158, the change is required to prevent possible
27 # display flickering issue.
28 register "disable_dynamic_tccold_handshake" = "true"
29
30 register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
31 .tdp_pl1_override = 18,
32 .tdp_pl2_override = 55,
33 .tdp_pl4 = 114,
34 }"
35
36 register "tcc_offset" = "6" # TCC of 94
37
38 register "platform_pmax" = "122"
39
40 register "usb2_ports[0]" = "{
41 .enable = 1,
42 .ocpin = OC0,
43 .pre_emp_bias = USB2_BIAS_28P15MV,
44 .tx_bias = USB2_BIAS_0MV,
45 .tx_emp_enable = USB2_PRE_EMP_ON,
46 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
47 .type_c = 1,
48 }" # USB2_C0
49 register "usb2_ports[1]" = "USB2_PORT_EMPTY"
50 register "usb2_ports[2]" = "{
51 .enable = 1,
52 .ocpin = OC_SKIP,
53 .pre_emp_bias = USB2_BIAS_28P15MV,
54 .tx_bias = USB2_BIAS_0MV,
55 .tx_emp_enable = USB2_PRE_EMP_ON,
56 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
57 .type_c = 1,
58 }" # USB2_C2
59 register "usb2_ports[3]" = "{
60 .enable = 1,
61 .ocpin = OC_SKIP,
62 .pre_emp_bias = USB2_BIAS_28P15MV,
63 .tx_bias = USB2_BIAS_0MV,
64 .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
65 .pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
66 }" # uSD
67 register "usb2_ports[4]" = "{
68 .enable = 1,
69 .ocpin = OC_SKIP,
70 .pre_emp_bias = USB2_BIAS_28P15MV,
71 .tx_bias = USB2_BIAS_11P25MV,
72 .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
73 .pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
74 }" # USB2_A1
75 register "usb2_ports[5]" = "{
76 .enable = 1,
77 .ocpin = OC_SKIP,
78 .pre_emp_bias = USB2_BIAS_28P15MV,
79 .tx_bias = USB2_BIAS_0MV,
80 .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
81 .pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
82 }" # Camera
83 register "usb2_ports[6]" = "USB2_PORT_EMPTY"
84 register "usb2_ports[7]" = "USB2_PORT_EMPTY"
85 register "usb2_ports[8]" = "USB2_PORT_EMPTY"
86 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
87
88 register "usb3_ports[0]" = "USB3_PORT_EMPTY"
89 register "usb3_ports[1]" = "USB3_PORT_EMPTY"
90 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_A1
91 register "usb3_ports[3]" = "USB3_PORT_EMPTY"
92
93 register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
94 register "tcss_ports[1]" = "TCSS_PORT_EMPTY"
95 register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
96 register "tcss_ports[3]" = "TCSS_PORT_EMPTY"
97
98 register "tcss_aux_ori" = "0x11"
99
100 register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
101 register "typec_aux_bias_pads[2]" = "{.pad_auxp_dc = GPP_A19, .pad_auxn_dc = GPP_A20}"
102
103 register "serial_io_i2c_mode" = "{
104 [PchSerialIoIndexI2C0] = PchSerialIoPci,
105 [PchSerialIoIndexI2C1] = PchSerialIoPci,
106 [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
107 [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
108 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
109 [PchSerialIoIndexI2C5] = PchSerialIoPci,
110 }"
111
112 register "serial_io_gspi_mode" = "{
113 [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
114 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
115 }"
116
117 # Intel Common SoC Config
118 #+-------------------+---------------------------+
119 #| Field | Value |
120 #+-------------------+---------------------------+
121 #| I2C0 | Audio |
122 #| I2C1 | cr50 TPM. Early init is |
123 #| | required to set up a BAR |
124 #| | for TPM communication |
125 #| I2C5 | Trackpad |
126 #+-------------------+---------------------------+
127 register "common_soc_config" = "{
128 .i2c[0]= {
129 .speed = I2C_SPEED_FAST,
130 .rise_time_ns = 175,
131 .fall_time_ns = 8,
132 },
133 .i2c[1] = {
134 .early_init = 1,
135 .speed = I2C_SPEED_FAST,
136 .rise_time_ns = 600,
137 .fall_time_ns = 400,
138 .data_hold_time_ns = 50,
139 },
140 .i2c[5] = {
141 .speed = I2C_SPEED_FAST,
142 .rise_time_ns = 650,
143 .fall_time_ns = 200,
144 .data_hold_time_ns = 50,
145 },
146 }"
147
148 device domain 0 on
149 device ref igpu on
150 chip drivers/gfx/generic
151 register "device_count" = "6"
152 # DDIA for eDP
153 register "device[0].name" = ""LCD""
154 # DDIB for HDMI
155 register "device[1].name" = ""DD01""
156 # TCP0 (DP-1) for port C0
157 register "device[2].name" = ""DD02""
158 register "device[2].use_pld" = "true"
159 register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
160 # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
161 register "device[3].name" = ""DD03""
162 # TCP2 (DP-3) for port C2
163 register "device[4].name" = ""DD04""
164 register "device[4].use_pld" = "true"
165 register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
166 # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
167 register "device[5].name" = ""DD05""
168 device generic 0 on end
169 end
170 end # Integrated Graphics Device
171 device ref dtt on
172 chip drivers/intel/dptf
173 ## sensor information
174 register "options.tsr[0].desc" = ""DRAM_SOC""
175 register "options.tsr[1].desc" = ""Ambient""
176 register "options.tsr[2].desc" = ""Charger""
177
178 # TODO: below values are initial reference values only
179 ## Active Policy
180 register "policies.active" = "{
181 [0] = {
182 .target = DPTF_TEMP_SENSOR_0,
183 .thresholds = {
184 TEMP_PCT(75, 97),
185 TEMP_PCT(70, 93),
186 TEMP_PCT(60, 86),
187 TEMP_PCT(52, 80),
188 TEMP_PCT(47, 64),
189 TEMP_PCT(43, 52),
190 TEMP_PCT(40, 40),
191 }
192 },
193 [1] = {
194 .target = DPTF_TEMP_SENSOR_1,
195 .thresholds = {
196 TEMP_PCT(75, 97),
197 TEMP_PCT(70, 93),
198 TEMP_PCT(60, 86),
199 TEMP_PCT(52, 80),
200 TEMP_PCT(47, 64),
201 TEMP_PCT(43, 52),
202 TEMP_PCT(40, 40),
203 }
204 },
205 [2] = {
206 .target = DPTF_TEMP_SENSOR_2,
207 .thresholds = {
208 TEMP_PCT(82, 97),
209 TEMP_PCT(78, 93),
210 TEMP_PCT(72, 86),
211 TEMP_PCT(60, 80),
212 }
213 }
214 }"
215
216 ## Passive Policy
217 register "policies.passive" = "{
218 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
219 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000),
220 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000),
221 [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
222 }"
223
224 ## Critical Policy
225 register "policies.critical" = "{
226 [0] = DPTF_CRITICAL(CPU, 99, SHUTDOWN),
227 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
228 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
229 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
230 }"
231
232 register "controls.power_limits" = "{
233 .pl1 = {
234 .min_power = 15000,
235 .max_power = 15000,
236 .time_window_min = 28 * MSECS_PER_SEC,
237 .time_window_max = 32 * MSECS_PER_SEC,
238 .granularity = 200,
239 },
240 .pl2 = {
241 .min_power = 55000,
242 .max_power = 55000,
243 .time_window_min = 28 * MSECS_PER_SEC,
244 .time_window_max = 32 * MSECS_PER_SEC,
245 .granularity = 1000,
246 }
247 }"
248
249 ## Charger Performance Control (Control, mA)
250 register "controls.charger_perf" = "{
251 [0] = { 255, 1700 },
252 [1] = { 24, 1500 },
253 [2] = { 16, 1000 },
254 [3] = { 8, 500 }
255 }"
256
257 ## Fan Performance Control (Percent, Speed, Noise, Power)
258 register "controls.fan_perf" = "{
259 [0] = { 90, 6700, 220, 2200, },
260 [1] = { 80, 5800, 180, 1800, },
261 [2] = { 70, 5000, 145, 1450, },
262 [3] = { 60, 4900, 115, 1150, },
263 [4] = { 50, 3838, 90, 900, },
264 [5] = { 40, 2904, 55, 550, },
265 [6] = { 30, 2337, 30, 300, },
266 [7] = { 20, 1608, 15, 150, },
267 [8] = { 10, 800, 10, 100, },
268 [9] = { 0, 0, 0, 50, }
269 }"
270
271 ## Fan options
272 register "options.fan.fine_grained_control" = "true"
273 register "options.fan.step_size" = "2"
274
275 device generic 0 alias dptf_policy on end
276 end
277 end
278 device ref pcie4_0 on
279 # Enable NVMe SSD using clk_src0 and clk_req1 mapping to hardware
280 # design. Due to inconsistency between PMC firmware and FSP, we need
281 # to set clk_src to clk_req number, not same as hardware mapping in
282 # coreboot. Then swap correct setting clksrc, clkreq in mFIT.
283 register "cpu_pcie_rp[CPU_RP(1)]" = "{
284 .clk_req = 1,
285 .clk_src = 1,
286 .flags = PCIE_RP_LTR | PCIE_RP_AER,
287 }"
288 probe STORAGE STORAGE_NVME
289 end # NVMe
290 device ref tbt_pcie_rp0 off end
291 device ref tbt_pcie_rp1 off end
292 device ref tbt_pcie_rp2 off end
293 device ref tbt_pcie_rp3 off end
294 device ref tcss_dma0 off end
295 device ref tcss_dma1 off end
296 device ref ish on
297 chip drivers/intel/ish
298 register "add_acpi_dma_property" = "true"
299 device generic 0 on end
300 end
301 probe STORAGE STORAGE_UFS
302 end
303 device ref ufs on
304 probe STORAGE STORAGE_UFS
305 end
306 device ref cnvi_wifi on
307 chip drivers/wifi/generic
308 register "wake" = "GPE0_PME_B0"
309 register "enable_cnvi_ddr_rfim" = "true"
310 device generic 0 on end
311 end
312 end
313 device ref i2c0 on
314 chip drivers/i2c/da7219
315 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
316 register "btn_cfg" = "50"
317 register "mic_det_thr" = "200"
318 register "jack_ins_deb" = "20"
319 register "jack_det_rate" = ""32ms_64ms""
320 register "jack_rem_deb" = "1"
321 register "a_d_btn_thr" = "0xa"
322 register "d_b_btn_thr" = "0x16"
323 register "b_c_btn_thr" = "0x21"
324 register "c_mic_btn_thr" = "0x3e"
325 register "btn_avg" = "4"
326 register "adc_1bit_rpt" = "1"
327 register "micbias_lvl" = "2600"
328 register "mic_amp_in_sel" = ""diff""
329 device i2c 1a on end
330 end
331 end #I2C0
332 device ref i2c1 on
333 chip drivers/i2c/tpm
334 register "hid" = ""GOOG0005""
335 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
336 device i2c 50 on end
337 end
338 end #I2C1
339 device ref i2c3 off end
340 device ref i2c5 on
341 chip drivers/i2c/hid
342 register "generic.hid" = ""ZNT0000""
343 register "generic.desc" = ""Zinitix Touchpad""
344 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
345 register "generic.wake" = "GPE0_DW2_14"
346 register "generic.detect" = "1"
347 register "hid_desc_reg_offset" = "0xE"
348 device i2c 40 on end
349 end
350 end #I2C5
351 device ref hda on
352 chip drivers/generic/max98357a
353 register "hid" = ""MX98360A""
354 register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
355 register "sdmode_delay" = "5"
356 device generic 0 on end
357 end
358 chip drivers/sof
359 register "spkr_tplg" = "max98360a"
360 register "jack_tplg" = "da7219"
361 register "mic_tplg" = "_2ch_pdm0"
362 device generic 0 on end
363 end
364
365 end
366 device ref pch_espi on
367 chip ec/google/chromeec
368 use conn0 as mux_conn[0]
369 use conn1 as mux_conn[1]
370 device pnp 0c09.0 on end
371 end
372 end
373 device ref sata off end
374 device ref pcie_rp8 off end
375 device ref pcie_rp9 off end
376 device ref gspi1 off end
377 device ref pmc hidden
378 chip drivers/intel/pmc_mux
379 device generic 0 on
380 chip drivers/intel/pmc_mux/conn
381 use usb2_port1 as usb2_port
382 use tcss_usb3_port1 as usb3_port
383 device generic 0 alias conn0 on end
384 end
385 chip drivers/intel/pmc_mux/conn
386 use usb2_port3 as usb2_port
387 use tcss_usb3_port3 as usb3_port
388 device generic 1 alias conn1 on end
389 end
390 end
391 end
392 end
393 device ref tcss_xhci on
394 chip drivers/usb/acpi
395 device ref tcss_root_hub on
396 chip drivers/usb/acpi
397 register "desc" = ""USB3 Type-C Port C0 (MLB)""
398 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
399 register "use_custom_pld" = "true"
400 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
401 device ref tcss_usb3_port1 on end
402 end
403 chip drivers/usb/acpi
404 register "desc" = ""USB3 Type-C Port C2 (MLB)""
405 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
406 register "use_custom_pld" = "true"
407 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
408 device ref tcss_usb3_port3 on end
409 end
410 end
411 end
412 end
413 device ref xhci on
414 chip drivers/usb/acpi
415 device ref xhci_root_hub on
416 chip drivers/usb/acpi
417 register "desc" = ""USB2 Type-C Port C0 (MLB)""
418 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
419 register "use_custom_pld" = "true"
420 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
421 device ref usb2_port1 on end
422 end
423 chip drivers/usb/acpi
424 register "desc" = ""USB2 Type-C Port C2 (MLB)""
425 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
426 register "use_custom_pld" = "true"
427 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
428 device ref usb2_port3 on end
429 end
430 chip drivers/usb/acpi
431 register "desc" = ""USB2 MMC""
432 register "type" = "UPC_TYPE_EXPRESSCARD"
433 device ref usb2_port4 on end
434 end
435 chip drivers/usb/acpi
436 register "desc" = ""USB2 Type-A Port A1 (DB)""
437 register "type" = "UPC_TYPE_A"
438 register "use_custom_pld" = "true"
439 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
440 device ref usb2_port5 on end
441 end
442 chip drivers/usb/acpi
443 register "desc" = ""USB2 Camera""
444 register "type" = "UPC_TYPE_INTERNAL"
445 device ref usb2_port6 on end
446 end
447 chip drivers/usb/acpi
448 register "desc" = ""USB2 Bluetooth""
449 register "type" = "UPC_TYPE_INTERNAL"
450 register "reset_gpio" =
451 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
452 device ref usb2_port10 on end
453 end
454 chip drivers/usb/acpi
455 register "desc" = ""USB3 Type-A Port A1 (DB)""
456 register "type" = "UPC_TYPE_USB3_A"
457 register "use_custom_pld" = "true"
458 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
459 device ref usb3_port3 on end
460 end
461 end
462 end
463 end
464 end
465 end
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