src/mainboard/google/cyan/com_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <device/mmio.h>
   5 #include <device/pci_ops.h>
   6 #include <soc/gpio.h>
   7 #include <soc/lpc.h>
   8 #include <soc/pci_devs.h>
   9
  10 void bootblock_mainboard_early_init(void)
  11 {
  12         uint32_t reg;
  13         uint32_t *pad_config_reg;
  14
  15         /* Enable the UART hardware for COM1. */
  16         reg = 1;
  17         pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg);
  18
  19         /*
  20          * Set up the pads to select the UART function
  21          * AD12 SW16(UART1_DATAIN/UART0_DATAIN)   - Set Mode 2 for UART0_RXD
  22          * AD10 SW20(UART1_DATAOUT/UART0_DATAOUT) - Set Mode 2 for UART0_TXD
  23          */
  24         pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_RXD_PAD);
  25         write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0,
  26                 M2));
  27
  28         pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_TXD_PAD);
  29         write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0,
  30                 M2));
  31 }