1 FLASH@0xff000000 0x1000000 {
6 SI_BIOS@0x381000 0xc7f000 {
7 RW_LEGACY(CBFS)@0x0 0x100000
8 RW_SECTION_A@0x100000 0x3a4800 {
10 FW_MAIN_A(CBFS)@0x2000 0x3a27c0
11 RW_FWID_A@0x3a47c0 0x40
13 RW_SECTION_B@0x4a4800 0x3a4800 {
15 FW_MAIN_B(CBFS)@0x2000 0x3a27c0
16 RW_FWID_B@0x3a47c0 0x40
18 RW_MISC@0x849000 0x36000 {
19 UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 {
20 RECOVERY_MRC_CACHE@0x0 0x10000
21 RW_MRC_CACHE@0x10000 0x20000
23 RW_ELOG(PRESERVE)@0x30000 0x1000
24 RW_SHARED@0x31000 0x1000 {
25 SHARED_DATA@0x0 0x1000
27 RW_VPD(PRESERVE)@0x32000 0x2000
28 RW_NVRAM(PRESERVE)@0x34000 0x2000
30 # Make WP_RO region align with SPI vendor
31 # memory protected range specification.
32 WP_RO@0x87f000 0x400000 {
33 RO_VPD(PRESERVE)@0x0 0x4000
34 RO_SECTION@0x4000 0x3fc000 {
37 RO_FRID_PAD@0x840 0x7c0
39 COREBOOT(CBFS)@0x4000 0x3f8000