src/mainboard/google/dedede/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <acpi/acpi.h>
   4 #include <acpi/acpigen.h>
   5 #include <baseboard/variants.h>
   6 #include <bootmode.h>
   7 #include <console/console.h>
   8 #include <delay.h>
   9 #include <device/device.h>
  10 #include <drivers/tpm/cr50.h>
  11 #include <ec/ec.h>
  12 #include <security/tpm/tss.h>
  13 #include <soc/soc_chip.h>
  14 #include <static.h>
  15 #include <timer.h>
  16 #include <vb2_api.h>
  17
  18 static void mainboard_update_soc_chip_config(void)
  19 {
  20         struct soc_intel_jasperlake_config *cfg = config_of_soc();
  21         tpm_result_t rc;
  22
  23         rc = tlcl_lib_init();
  24         if (rc != TPM_SUCCESS) {
  25                 printk(BIOS_ERR, "tlcl_lib_init() failed: %#x\n", rc);
  26                 return;
  27         }
  28
  29         if (!cr50_is_long_interrupt_pulse_enabled()) {
  30                 /* Disable GPIO PM to allow for shorter IRQ pulses */
  31                 printk(BIOS_INFO, "Override GPIO PM\n");
  32                 cfg->gpio_override_pm = 1;
  33                 memset(cfg->gpio_pm, 0, sizeof(cfg->gpio_pm));
  34         }
  35 }
  36
  37 static bool any_hpd_ready(const gpio_t *gpios, size_t num_gpios)
  38 {
  39         for (size_t i = 0; i < num_gpios; i++) {
  40                 if (gpio_get(gpios[i]))
  41                         return true;
  42         }
  43
  44         return false;
  45 }
  46
  47 static void mainboard_wait_for_hpd(void)
  48 {
  49         static const long display_timeout_ms = 3000;
  50         struct stopwatch sw;
  51         size_t num_gpios;
  52         const gpio_t *hpd_gpios = variant_hpd_gpios(&num_gpios);
  53
  54         if (num_gpios == 0) {
  55                 printk(BIOS_WARNING, "No HPD GPIOs, skip waiting\n");
  56                 return;
  57         }
  58
  59         printk(BIOS_INFO, "Waiting for HPD\n");
  60
  61         /* Pins will be configured back by gpio_configure_pads. */
  62         for (size_t i = 0; i < num_gpios; i++) {
  63                 gpio_input(hpd_gpios[i]);
  64         }
  65
  66         stopwatch_init_msecs_expire(&sw, display_timeout_ms);
  67         while (!any_hpd_ready(hpd_gpios, num_gpios)) {
  68                 if (stopwatch_expired(&sw)) {
  69                         printk(BIOS_WARNING,
  70                                "HPD not ready after %ld ms. Abort.\n",
  71                                display_timeout_ms);
  72                         return;
  73                 }
  74                 mdelay(200);
  75         }
  76         printk(BIOS_INFO, "HPD ready after %lld ms\n",
  77                stopwatch_duration_msecs(&sw));
  78 }
  79
  80 static void mainboard_init(void *chip_info)
  81 {
  82         const struct pad_config *base_pads;
  83         const struct pad_config *override_pads;
  84         size_t base_num, override_num;
  85
  86         /*
  87          * For chromeboxes, wait for DP HPD to be asserted before
  88          * entering FSP-S, otherwise display init may fail.
  89          */
  90         if (!CONFIG(SYSTEM_TYPE_LAPTOP) && display_init_required())
  91                 mainboard_wait_for_hpd();
  92
  93         base_pads = baseboard_gpio_table(&base_num);
  94         override_pads = variant_override_gpio_table(&override_num);
  95
  96         gpio_configure_pads_with_override(base_pads, base_num,
  97                 override_pads, override_num);
  98
  99         variant_devtree_update();
 100
 101         if (CONFIG(BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50))
 102                 mainboard_update_soc_chip_config();
 103 }
 104
 105 void __weak variant_devtree_update(void)
 106 {
 107         /* Override dev tree settings per board */
 108 }
 109
 110 static void mainboard_dev_init(struct device *dev)
 111 {
 112         mainboard_ec_init();
 113 }
 114
 115 static unsigned long mainboard_write_acpi_tables(
 116                 const struct device *device, unsigned long current, acpi_rsdp_t *rsdp)
 117 {
 118         return current;
 119 }
 120
 121 static void mainboard_generate_s0ix_hook(void)
 122 {
 123         acpigen_write_if_lequal_op_int(ARG0_OP, 1);
 124         variant_generate_s0ix_hook(S0IX_ENTRY);
 125         acpigen_write_else();
 126         variant_generate_s0ix_hook(S0IX_EXIT);
 127         acpigen_write_if_end();
 128 }
 129
 130 static void mainboard_fill_ssdt(const struct device *dev)
 131 {
 132         acpigen_write_scope("\\_SB");
 133         acpigen_write_method_serialized("MS0X", 1);
 134         mainboard_generate_s0ix_hook();
 135         acpigen_write_method_end(); /* Method */
 136         acpigen_write_scope_end(); /* Scope */
 137 }
 138
 139 void __weak variant_generate_s0ix_hook(enum s0ix_entry entry)
 140 {
 141         /* Add board-specific MS0X entries */
 142         /*
 143         if (s0ix_entry == S0IX_ENTRY) {
 144                 implement variant operations here
 145         }
 146         if (s0ix_entry == S0IX_EXIT) {
 147                 implement variant operations here
 148         }
 149         */
 150 }
 151
 152
 153 static void mainboard_enable(struct device *dev)
 154 {
 155         dev->ops->init = mainboard_dev_init;
 156         dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
 157         dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
 158 }
 159
 160 struct chip_operations mainboard_ops = {
 161         .init = mainboard_init,
 162         .enable_dev = mainboard_enable,
 163 };