src/mainboard/google/dedede/variants/baseboard/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/variants.h>
   4 #include <baseboard/gpio.h>
   5 #include <gpio.h>
   6 #include <soc/meminit.h>
   7 #include <soc/romstage.h>
   8
   9 static const struct mb_cfg baseboard_memcfg_cfg = {
  10         .dq_map[DDR_CH0] = {
  11                 {0xf, 0xf0},
  12                 {0xf, 0xf0},
  13                 {0xff, 0x0},
  14                 {0x0, 0x0},
  15                 {0x0, 0x0},
  16                 {0x0, 0x0}
  17         },
  18         .dq_map[DDR_CH1] = {
  19                 {0xf, 0xf0},
  20                 {0xf, 0xf0},
  21                 {0xff, 0x0},
  22                 {0x0, 0x0},
  23                 {0x00, 0x0},
  24                 {0x00, 0x0}
  25         },
  26
  27         /*
  28          * The dqs_map arrays map the ddr4 pins to the SoC pins
  29          * for both channels.
  30          *
  31          * the index = pin number on SoC
  32          * the value = pin number on LPDDR4 part
  33          */
  34
  35         .dqs_map[DDR_CH0] = {1, 3, 0, 2, 7, 5, 4, 6},
  36         .dqs_map[DDR_CH1] = {3, 1, 2, 0, 4, 5, 7, 6},
  37
  38         /* Disable Early Command Training */
  39         .ect = 1,
  40
  41         /* User Board Type */
  42         .UserBd = BOARD_TYPE_MOBILE,
  43 };
  44
  45 const struct mb_cfg *__weak variant_memcfg_config(void)
  46 {
  47         return &baseboard_memcfg_cfg;
  48 }
  49
  50 int __weak variant_memory_sku(void)
  51 {
  52         gpio_t spd_gpios[] = {
  53                 GPIO_MEM_CONFIG_0,
  54                 GPIO_MEM_CONFIG_1,
  55                 GPIO_MEM_CONFIG_2,
  56                 GPIO_MEM_CONFIG_3,
  57         };
  58
  59         return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
  60 }
  61
  62 bool __weak variant_mem_is_half_populated(void)
  63 {
  64         return !gpio_get(GPIO_MEM_CH_SEL);
  65 }