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libpayload: configs: Add new config.featuretest to broaden CI
[coreboot2.git] / src / mainboard / google / dedede / variants / dita / overridetree.cb
blobf53a11a89e43d49c01e90d2a7e51bbc16cf5eb3e
1 chip soc/intel/jasperlake
2
3 # Intel Common SoC Config
4 #+-------------------+---------------------------+
5 #| Field | Value |
6 #+-------------------+---------------------------+
7 #| GSPI0 | cr50 TPM. Early init is |
8 #| | required to set up a BAR |
9 #| | for TPM communication |
10 #| | before memory is up |
11 #| I2C4 | Audio |
12 #+-------------------+---------------------------+
13 register "common_soc_config" = "{
14 .gspi[0] = {
15 .speed_mhz = 1,
16 .early_init = 1,
17 },
18 .i2c[4] = {
19 .speed_config[0] = {
20 .speed = I2C_SPEED_FAST,
21 .scl_lcnt = 190,
22 .scl_hcnt = 100,
23 .sda_hold = 40,
24 }
25 },
26 }"
27
28 # Power limit config
29 register "power_limits_config[JSL_N4500_6W_CORE]" = "{
30 .tdp_pl1_override = 6,
31 .tdp_pl2_override = 20,
32 .tdp_pl4 = 60,
33 }"
34
35 register "power_limits_config[JSL_N5100_6W_CORE]" = "{
36 .tdp_pl1_override = 6,
37 .tdp_pl2_override = 20,
38 .tdp_pl4 = 60,
39 }"
40
41 # Root Port 3 (index 2) for LAN
42 # External PCIe port 7 is mapped to PCIe Root Port 3
43 register "PcieClkSrcUsage[4]" = "2"
44
45 # Root Port 7 (index 6) for WLAN
46 # External PCIe port 3 is mapped to PCIe Root Port 7
47 register "PcieClkSrcUsage[3]" = "6"
48
49 # Audio related configurations
50 register "PchHdaAudioLinkDmicEnable[0]" = "0"
51 register "PchHdaAudioLinkDmicEnable[1]" = "0"
52
53 # Disable SD card
54 register "sdcard_cd_gpio" = "0"
55 register "SdCardPowerEnableActiveHigh" = "0"
56
57 # Disable eDP on port A
58 register "DdiPortAConfig" = "0"
59
60 # Enable HPD and DDC for DDI port A
61 register "DdiPortAHpd" = "1"
62 register "DdiPortADdc" = "1"
63
64 # Does not support external vnn power rail
65 register "disable_external_bypass_vr" = "1"
66
67 # USB Port Configuration
68 register "usb2_ports[0]" = "{
69 .enable = 1,
70 .ocpin = OC_SKIP,
71 .tx_bias = USB2_BIAS_0MV,
72 .tx_emp_enable = USB2_PRE_EMP_ON,
73 .pre_emp_bias = USB2_BIAS_11P25MV,
74 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
75 }" # Type-C Port 0
76 register "usb2_ports[1]" = "{
77 .enable = 1,
78 .ocpin = OC1,
79 .tx_bias = USB2_BIAS_0MV,
80 .tx_emp_enable = USB2_PRE_EMP_ON,
81 .pre_emp_bias = USB2_BIAS_11P25MV,
82 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
83 }" # Type-A Port A0
84 register "usb2_ports[2]" = "{
85 .enable = 1,
86 .ocpin = OC2,
87 .tx_bias = USB2_BIAS_0MV,
88 .tx_emp_enable = USB2_PRE_EMP_ON,
89 .pre_emp_bias = USB2_BIAS_11P25MV,
90 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
91 }" # Type-A Port A1
92 register "usb2_ports[3]" = "{
93 .enable = 1,
94 .ocpin = OC3,
95 .tx_bias = USB2_BIAS_0MV,
96 .tx_emp_enable = USB2_PRE_EMP_ON,
97 .pre_emp_bias = USB2_BIAS_11P25MV,
98 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
99 }" # Type-A Port A2
100 register "usb2_ports[4]" = "{
101 .enable = 1,
102 .ocpin = OC0,
103 .tx_bias = USB2_BIAS_0MV,
104 .tx_emp_enable = USB2_PRE_EMP_ON,
105 .pre_emp_bias = USB2_BIAS_11P25MV,
106 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
107 }" # Type-A Port A3
108 register "usb2_ports[6]" = "{
109 .enable = 1,
110 .ocpin = OC_SKIP,
111 .tx_bias = USB2_BIAS_0MV,
112 .tx_emp_enable = USB2_PRE_EMP_ON,
113 .pre_emp_bias = USB2_BIAS_11P25MV,
114 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
115 }" # Type-A Port A4
116
117 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A4
118 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A2
119 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A3
120
121 # Bitmap for Wake Enable on USB attach/detach
122 register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
123 USB_PORT_WAKE_ENABLE(2) |
124 USB_PORT_WAKE_ENABLE(3) |
125 USB_PORT_WAKE_ENABLE(4) |
126 USB_PORT_WAKE_ENABLE(5) |
127 USB_PORT_WAKE_ENABLE(7)"
128 register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
129 USB_PORT_WAKE_ENABLE(2) |
130 USB_PORT_WAKE_ENABLE(3) |
131 USB_PORT_WAKE_ENABLE(4) |
132 USB_PORT_WAKE_ENABLE(5) |
133 USB_PORT_WAKE_ENABLE(6)"
134
135 device domain 0 on
136 device pci 04.0 on
137 chip drivers/intel/dptf
138 ## Passive Policy
139 register "policies.passive" = "{
140 [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000),
141 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000),
142 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 15000),
143 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 55, 15000)
144 }"
145
146 ## Critical Policy
147 register "policies.critical" = "{
148 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
149 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN),
150 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN),
151 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN)
152 }"
153
154 register "controls.power_limits" = "{
155 .pl1 = {
156 .min_power = 3000,
157 .max_power = 6000,
158 .time_window_min = 1 * MSECS_PER_SEC,
159 .time_window_max = 1 * MSECS_PER_SEC,
160 .granularity = 100,
161 },
162 .pl2 = {
163 .min_power = 20000,
164 .max_power = 20000,
165 .time_window_min = 1 * MSECS_PER_SEC,
166 .time_window_max = 1 * MSECS_PER_SEC,
167 .granularity = 1000,
168 }
169 }"
170
171 register "options.tsr[0].desc" = ""Memory""
172 register "options.tsr[1].desc" = ""Power""
173 register "options.tsr[2].desc" = ""Chassis""
174
175 ## Charger Performance Control (Control, mA)
176 register "controls.charger_perf" = "{
177 [0] = { 255, 3000 },
178 [1] = { 24, 1500 },
179 [2] = { 16, 1000 },
180 [3] = { 8, 500 }
181 }"
182
183 device generic 0 on end
184 end
185 end # SA Thermal device
186 device pci 14.0 on
187 chip drivers/usb/acpi
188 device usb 0.0 on
189 chip drivers/usb/acpi
190 register "desc" = ""USB2 Type-C Port C0""
191 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
192 register "group" = "ACPI_PLD_GROUP(2, 1)"
193 device usb 2.0 on end
194 end
195 chip drivers/usb/acpi
196 register "desc" = ""USB2 Type-A Port A0""
197 register "type" = "UPC_TYPE_A"
198 register "group" = "ACPI_PLD_GROUP(2, 2)"
199 device usb 2.1 on end
200 end
201 chip drivers/usb/acpi
202 register "desc" = ""USB2 Type-A Port A1""
203 register "type" = "UPC_TYPE_A"
204 register "group" = "ACPI_PLD_GROUP(2, 3)"
205 device usb 2.2 on end
206 end
207 chip drivers/usb/acpi
208 register "desc" = ""USB2 Type-A Port A2""
209 register "type" = "UPC_TYPE_A"
210 register "group" = "ACPI_PLD_GROUP(1, 3)"
211 device usb 2.3 on end
212 end
213 chip drivers/usb/acpi
214 register "desc" = ""USB2 Type-A Port A3""
215 register "type" = "UPC_TYPE_A"
216 register "group" = "ACPI_PLD_GROUP(1, 2)"
217 device usb 2.4 on end
218 end
219 chip drivers/usb/acpi
220 register "desc" = ""USB2 Type-A Port A4""
221 register "type" = "UPC_TYPE_A"
222 register "group" = "ACPI_PLD_GROUP(1, 1)"
223 device usb 2.6 on end
224 end
225 chip drivers/usb/acpi
226 register "desc" = ""USB3 Type-C Port C0""
227 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
228 register "group" = "ACPI_PLD_GROUP(2, 1)"
229 device usb 3.0 on end
230 end
231 chip drivers/usb/acpi
232 register "desc" = ""USB3 Type-A Port A4""
233 register "type" = "UPC_TYPE_USB3_A"
234 register "group" = "ACPI_PLD_GROUP(1, 1)"
235 device usb 3.1 on end
236 end
237 chip drivers/usb/acpi
238 register "desc" = ""USB3 Type-A Port A0""
239 register "type" = "UPC_TYPE_USB3_A"
240 register "group" = "ACPI_PLD_GROUP(2, 2)"
241 device usb 3.2 on end
242 end
243 chip drivers/usb/acpi
244 register "desc" = ""USB3 Type-A Port A1""
245 register "type" = "UPC_TYPE_USB3_A"
246 register "group" = "ACPI_PLD_GROUP(2, 3)"
247 device usb 3.3 on end
248 end
249 chip drivers/usb/acpi
250 register "desc" = ""USB3 Type-A Port A3""
251 register "type" = "UPC_TYPE_USB3_A"
252 register "group" = "ACPI_PLD_GROUP(1, 2)"
253 device usb 3.4 on end
254 end
255 chip drivers/usb/acpi
256 register "desc" = ""USB3 Type-A Port A2""
257 register "type" = "UPC_TYPE_USB3_A"
258 register "group" = "ACPI_PLD_GROUP(1, 3)"
259 device usb 3.5 on end
260 end
261 end
262 end
263 end # USB xHCI
264 device pci 15.0 off end # I2C 0
265 device pci 15.1 off end # I2C 1
266 device pci 15.2 off end # I2C 2
267 device pci 15.3 off end # I2C 3
268 device pci 19.0 on
269 chip drivers/i2c/generic
270 register "hid" = ""RTL5682""
271 register "name" = ""RT58""
272 register "desc" = ""Realtek RT5682""
273 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
274 register "property_count" = "1"
275 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
276 register "property_list[0].name" = ""realtek,jd-src""
277 register "property_list[0].integer" = "1"
278 device i2c 1a on end
279 end
280 end # I2C 4
281 device pci 1c.2 on
282 chip drivers/net
283 register "customized_leds" = "0x05af"
284 register "wake" = "GPE0_DW0_03" # GPP_B3
285 register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
286 register "device_index" = "0"
287 device pci 00.0 on end
288 end
289 end # PCI Express Root Port 3 - RTL8111H LAN
290 device pci 1c.6 on
291 chip drivers/wifi/generic
292 register "wake" = "GPE0_DW2_03"
293 device pci 00.0 on end
294 end
295 end # PCI Express Root Port 7 - WLAN
296 device pci 1c.7 off end # PCI Express Root Port 8
297 device pci 1f.3 on end # Intel HDA
298 end
299 end
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