soc/mediatek/mt8196: Initialize SSPM
[coreboot2.git] / src / mainboard / google / dedede / variants / drawcia / gpio.c
blobd42b38e6d24aa5f47606e17c33ee3565ea637d58
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 #include <boardid.h>
6 #include <bootstate.h>
7 #include <fw_config.h>
8 #include <ec/google/chromeec/ec.h>
10 /* Pad configuration in ramstage */
11 static const struct pad_config not_board6or8_gpio_table[] = {
12 /* C12 : AP_PEN_DET_ODL */
13 PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, UP_20K, DEEP),
16 /* bid6: Pad configuration for board version 6 or 8 in ramstage */
17 static const struct pad_config board6or8_gpio_table[] = {
18 /* A10 : WWAN_EN */
19 PAD_CFG_GPO(GPP_A10, 1, PWROK),
21 /* B7 : PCIE_CLKREQ2_N ==> WWAN_SAR_DETECT_ODL*/
22 PAD_CFG_GPO(GPP_B7, 1, DEEP),
24 /* C12 : AP_PEN_DET_ODL has an external pull-up and hence no pad termination.*/
25 PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),
27 /* D0 : WWAN_HOST_WAKE ==> WWAN_WDISABLE_L */
28 PAD_CFG_GPO(GPP_D0, 1, DEEP),
30 /* H0 : WWAN_PERST */
31 PAD_CFG_GPO(GPP_H0, 0, PLTRST),
32 PAD_CFG_GPO(GPP_H17, 0, PLTRST),
35 static const struct pad_config lte_disable_pads[] = {
36 PAD_NC(GPP_A10, NONE),
37 PAD_NC(GPP_B7, NONE),
38 PAD_NC(GPP_D0, NONE),
39 PAD_NC(GPP_H0, NONE),
40 PAD_NC(GPP_H17, NONE),
43 const struct pad_config *variant_override_gpio_table(size_t *num)
45 uint32_t board_version = board_id();
46 *num = ARRAY_SIZE(not_board6or8_gpio_table);
48 if (board_version == 6 || board_version >= 8) {
49 *num = ARRAY_SIZE(board6or8_gpio_table);
50 return board6or8_gpio_table;
53 return not_board6or8_gpio_table;
56 static void fw_config_handle(void *unused)
58 if (!fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1A_HDMI_LTE)))
59 gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads));
61 BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);