src/mainboard/google/fatcat/variants/francka/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <boardid.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage*/
   9 static const struct pad_config gpio_table[] = {
  10         /* GPP_A00:     ESPI_IO0_EC_R */
  11         /*  GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
  12
  13         /* GPP_A01:     ESPI_IO1_EC_R */
  14         /*  GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
  15
  16         /* GPP_A02:     ESPI_IO2_EC_R */
  17         /*  GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
  18
  19         /* GPP_A03:     ESPI_IO3_EC_R */
  20         /*  GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
  21
  22         /* GPP_A04:     ESPI_CS0_EC_R_N */
  23         /*  GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
  24
  25         /* GPP_A05:     ESPI_CLK_EC_R */
  26         /*  GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
  27
  28         /* GPP_A06:     ESPI_RST_EC_R_N */
  29         /*  GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
  30
  31         /* GPP_A08:     SOC_SD_PWR_EN */
  32         PAD_CFG_GPO(GPP_A08, 1, PLTRST),
  33         /* GPP_A09:     SOC_WWAN_OFF#_SW */
  34         PAD_CFG_GPO(GPP_A09, 1, PLTRST),
  35         /* GPP_A10:     SOC_WWAN_RA_DIS#_SW */
  36         PAD_CFG_GPO(GPP_A10, 1, PLTRST),
  37         /* GPP_A11:     Not used */
  38         PAD_NC(GPP_A11, NONE),
  39         /* GPP_A12:     Not used */
  40         PAD_NC(GPP_A12, NONE),
  41         /* GPP_A13:     Not used */
  42         PAD_NC(GPP_A13, NONE),
  43         /* GPP_A15:     Not used */
  44         PAD_NC(GPP_A15, NONE),
  45         /* GPP_A16:     SOC_BT_ON */
  46         PAD_CFG_GPO(GPP_A16, 1, DEEP),
  47         /* GPP_A17:     SOC_WL_OFF# */
  48         PAD_CFG_GPO(GPP_A17, 1, DEEP),
  49
  50         /* GPP_B00:     SOC_USBC_SMLCLK */
  51         PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
  52         /* GPP_B01:     SOC_USBC_SMLDATA */
  53         PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
  54         /* GPP_B02:     ISH_I2C_0_SDA */
  55         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
  56         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3),
  57         /* GPP_B03:     ISH_I2C_0_SCL */
  58         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
  59         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
  60         /* GPP_B04:     Not used */
  61         PAD_NC(GPP_B04, NONE),
  62         /* GPP_B05:     SOC_EC_INT# */
  63         PAD_CFG_GPI_APIC(GPP_B05, NONE, PLTRST, LEVEL, INVERT),
  64         /* GPP_B06:     Not used */
  65         PAD_NC(GPP_B06, NONE),
  66         /* GPP_B07:     SOC_CODEC_RST# */
  67         PAD_NC(GPP_B07, NONE),
  68         /* GPP_B08:     SOC_TP_RST#1 */
  69         PAD_CFG_GPO(GPP_B08, 1, PLTRST),
  70         /* GPP_B09:     SOC_TCP0_DP_HPD# */
  71         PAD_CFG_NF(GPP_B09, NONE, DEEP, NF2),
  72         /* GPP_B10:     SOC_TCP1_DP_HPD# */
  73         PAD_CFG_NF(GPP_B10, NONE, DEEP, NF2),
  74         /* GPP_B11:     SOC_RTS_P0_P1_OC# */
  75         PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
  76         /* GPP_B12:     PM_SLP_S0# */
  77         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  78         /* GPP_B13:     SOC_PLTRST# */
  79         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  80         /* GPP_B14:     Not used */
  81         PAD_NC(GPP_B14, NONE),
  82         /* GPP_B15:     Not used */
  83         PAD_NC(GPP_B15, NONE),
  84         /* GPP_B16:     SOC_SSD2_EN */
  85         PAD_CFG_GPO(GPP_B16, 1, PLTRST),
  86         /* GPP_B17:     SOC_ENVDD2 */
  87         PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
  88         /* GPP_B18:     TCHSCR_REPORT_DISABLE */
  89         PAD_CFG_GPO(GPP_B18, 0, PLTRST),
  90         /* GPP_B19:     SOC_CNVI_EN# */
  91         PAD_CFG_GPO(GPP_B19, 0, PLTRST),
  92         /* GPP_B20:     SOC_WWAN_RST# */
  93         PAD_CFG_GPO(GPP_B20, 1, PLTRST),
  94         /* GPP_B21:     SOC_RT_FORCE_PWR */
  95         PAD_CFG_GPO(GPP_B21, 0, DEEP),
  96         /* GPP_B22:     SEN_MODE_EC_PCH_INT_OD# */
  97         PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
  98         /* GPP_B23:     Not used */
  99         PAD_NC(GPP_B23, NONE),
 100         /* GPP_B24:     Not used */
 101         PAD_NC(GPP_B24, NONE),
 102         /* GPP_B25:     SOC_SD_WAKE# */
 103         PAD_CFG_GPI_SCI_LOW(GPP_B25, NONE, DEEP, LEVEL),
 104
 105         /* GPP_C00:     SOC_SMBCLK */
 106         PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
 107         /* GPP_C01:     SOC_SMBDATA */
 108         PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
 109         /* GPP_C02:     Not used */
 110         PAD_NC(GPP_C02, NONE),
 111         /* GPP_C03:     SOC_SML0CLK */
 112         PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
 113         /* GPP_C04:     SOC_SML0DATA */
 114         PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
 115         /* GPP_C05:     Not used */
 116         PAD_NC(GPP_C05, NONE),
 117         /* GPP_C06:     Not used */
 118         PAD_NC(GPP_C06, NONE),
 119         /* GPP_C07:     Not used */
 120         PAD_NC(GPP_C07, NONE),
 121         /* GPP_C08:     Not used */
 122         PAD_NC(GPP_C08, NONE),
 123         /* GPP_C09:     Not used */
 124         PAD_NC(GPP_C09, NONE),
 125         /* GPP_C10:     CLKREQ_PCIE#1 */
 126         PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
 127         /* GPP_C11:     CLKREQ_PCIE#2 */
 128         PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
 129         /* GPP_C12:     Not used */
 130         PAD_NC(GPP_C12, NONE),
 131         /* GPP_C13:     CLKREQ_PCIE#4 */
 132         PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
 133         /* GPP_C14:     CLKREQ_PCIE#5 */
 134         PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
 135         /* GPP_C15:     Not used */
 136         PAD_NC(GPP_C15, NONE),
 137         /* GPP_C16:     TBT_0_LSX_TX  */
 138         PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 139         /* GPP_C17:     TBT_0_LSX_RX  */
 140         PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
 141         /* GPP_C18:     TBT_1_LSX_TX  */
 142         PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 143         /* GPP_C19:     TBT_2_LSX_RX */
 144         PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 145         /* GPP_C20:     TBT_2_LSX_TX */
 146         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 147         /* GPP_C21:     TBT_2_LSX_RX */
 148         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 149         /* GPP_C22:     TBT_3_LSX_TX */
 150         PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
 151         /* GPP_C23:     TBT_3_LSX_RX */
 152         PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
 153
 154         /* GPP_D00:     SOC_SD_PRSNT# */
 155         PAD_CFG_GPO(GPP_D00, 1, PLTRST),
 156         /* GPP_D01:     Not used */
 157         PAD_NC(GPP_D01, NONE),
 158         /* GPP_D02:     Not used */
 159         PAD_NC(GPP_D02, NONE),
 160         /* GPP_D03:     SOC_WWAN_PCIE_RST# */
 161         PAD_CFG_GPO(GPP_D03, 1, PLTRST),
 162         /* GPP_D04:     IPCM_SLOW */
 163         PAD_CFG_GPO(GPP_D04, 1, PLTRST),
 164         /* GPP_D05:     Not used */
 165         PAD_NC(GPP_D05, NONE),
 166         /* GPP_D06:     Not used */
 167         PAD_NC(GPP_D06, NONE),
 168         /* GPP_D07:     DDR_STRAP_2 */
 169         PAD_CFG_GPI(GPP_D07, NONE, DEEP),
 170         /* GPP_D08:     DDR_STRAP_1 */
 171         PAD_CFG_GPI(GPP_D08, NONE, DEEP),
 172         /* GPP_D09:     PCH_DGPU_HOLD_RST#_R */
 173         PAD_NC(GPP_D09, NONE),
 174         /* GPP_D10:     HDA_BIT_CLK */
 175         PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
 176         /* GPP_D11:     HDA_SYNC */
 177         PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
 178         /* GPP_D12:     HDA_SDOUT */
 179         PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
 180         /* GPP_D13:     HDA_SDIN0 */
 181         PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
 182         /* GPP_D14:     SOC_HDMI_STRAP */
 183         PAD_CFG_GPI(GPP_D14, NONE, DEEP),
 184         /* GPP_D15:     Not used */
 185         PAD_NC(GPP_D15, NONE),
 186         /* GPP_D16:     HDA_RST# */
 187         PAD_NC(GPP_D16, NONE),
 188         /* GPP_D17:     FPMCU_INT# */
 189         PAD_CFG_GPI_INT(GPP_D17, NONE, PLTRST, LEVEL),
 190         /* GPP_D18:     CLKREQ_PCIE#6 */
 191         PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
 192         /* GPP_D19:     SOC_SD_RST# */
 193         PAD_CFG_GPO(GPP_D19, 1, PLTRST),
 194         /* GPP_D20:     CSE_EARLY_SW */
 195         PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL),
 196         /* GPP_D21:     Not used */
 197         PAD_NC(GPP_D21, NONE),
 198         /* GPP_D22:     SOC_I3C_BPK_SDA */
 199         PAD_CFG_NF(GPP_D22, NONE, DEEP, NF2),
 200         /* GPP_D23:     SOC_I3C_BPK_SCL */
 201         PAD_CFG_NF(GPP_D23, NONE, DEEP, NF2),
 202         /* GPP_D24:     Not used */
 203         PAD_NC(GPP_D24, NONE),
 204         /* GPP_D25:     Not used */
 205         PAD_NC(GPP_D25, NONE),
 206
 207         /* GPP_E01:     SOC_TP_INT#1 */
 208         PAD_CFG_GPI_APIC(GPP_E01, NONE, PLTRST, LEVEL, INVERT),
 209         /* GPP_E02:     SOC_WWAN_WAKE2#_R  */
 210         PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL),
 211         /* GPP_E03:     SOC_SSD2_RST# */
 212         PAD_CFG_GPO(GPP_E03, 1, PLTRST),
 213         /* GPP_E05:     Not used */
 214         PAD_NC(GPP_E05, NONE),
 215         /* GPP_E06:     Not used */
 216         PAD_NC(GPP_E06, NONE),
 217         /* GPP_E07:     Not used */
 218         PAD_NC(GPP_E07, NONE),
 219         /* GPP_E08:     Not used*/
 220         PAD_NC(GPP_E08, NONE),
 221         /* GPP_E09:     USB_OC0# */
 222         PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
 223         /* GPP_E10:     Not used */
 224         PAD_NC(GPP_E10, NONE),
 225         /* GPP_E11:     Not used */
 226         PAD_NC(GPP_E11, NONE),
 227         /* GPP_E12:     SOC_THC_I2C_0_SCL */
 228         PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),
 229         /* GPP_E13:     SOC_THC_I2C_0_SDA */
 230         PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8),
 231         /* GPP_E14:     Not used */
 232         PAD_NC(GPP_E14, NONE),
 233         /* GPP_E15:     Not used */
 234         PAD_NC(GPP_E15, NONE),
 235         /* GPP_E16:     Not used */
 236         /* THC NOTE: use GPO instead of GPO for THC0 Rst */
 237         PAD_NC(GPP_E16, NONE),
 238         /* GPP_E17:     Not used */
 239         PAD_NC(GPP_E17, NONE),
 240         /* GPP_E18:     SOC_TP_INT# */
 241         PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, EDGE_SINGLE, INVERT),
 242         /* GPP_E19:     Not used */
 243         PAD_NC(GPP_E19, NONE),
 244         /* GPP_E20:     Not used# */
 245         PAD_NC(GPP_E20, NONE),
 246         /* GPP_E21:     SOC_I2C_PD_INT# */
 247         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
 248         /* GPP_E22:     SOC_WP_OD */
 249         PAD_CFG_GPI(GPP_E22, NONE, DEEP),
 250
 251         /* GPP_F00:     M.2_CNV_BRI_DT_BT_UART2_RTS_N */
 252         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 253         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
 254         /* GPP_F01:     M.2_CNV_BRI_RSP_BT_UART2_RXD */
 255         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 256         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
 257         /* GPP_F02:     M.2_CNV_RGI_DT_BT_UART2_TXD */
 258         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 259         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
 260         /* GPP_F03:     M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
 261         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 262         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
 263         /* GPP_F04:     CNV_RF_RESET_R_N */
 264         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 265         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
 266         /* GPP_F05:     CRF_CLKREQ_R */
 267         /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
 268         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
 269         /* GPP_F06:     COEX3 */
 270         PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
 271         /* GPP_F07:     Not used */
 272         PAD_NC(GPP_F07, NONE),
 273         /* GPP_F08:     Not used */
 274         PAD_NC(GPP_F08, NONE),
 275         /* GPP_F09:     SX_EXIT_HOLDOFF# */
 276         PAD_CFG_NF(GPP_F09, NONE, DEEP, NF2),
 277         /* GPP_F10:     Not used */
 278         PAD_NC(GPP_F10, NONE),
 279         /* GPP_F11:     SOC_THC_1_CLK */
 280         PAD_CFG_NF(GPP_F11, NONE, DEEP, NF5),
 281         /* GPP_F12:     SOC_THC_1_D0 */
 282         PAD_CFG_NF(GPP_F12, NONE, DEEP, NF5),
 283         /* GPP_F13:     SOC_THC_1_D1 */
 284         PAD_CFG_NF(GPP_F13, NONE, DEEP, NF5),
 285         /* GPP_F14:     Not used */
 286         PAD_NC(GPP_F14, NONE),
 287         /* GPP_F15:     Not used */
 288         PAD_NC(GPP_F15, NONE),
 289         /* GPP_F16:     SOC_THC_1_RST# */
 290         PAD_CFG_GPO(GPP_F16, 0, DEEP),
 291         /* GPP_F17:     SOC_THC_1_CS# */
 292         PAD_CFG_NF(GPP_F17, NONE, DEEP, NF5),
 293         /* GPP_F18:     SOC_THC_1_INT# */
 294         PAD_CFG_GPI_APIC(GPP_F18, NONE, PWROK, LEVEL, INVERT),
 295         /* GPP_F19:     Not used */
 296         PAD_NC(GPP_F19, NONE),
 297         /* GPP_F20:     AP_FP_FW_UP_STRAP */
 298         PAD_CFG_GPO(GPP_F20, 1, DEEP),
 299         /* GPP_F22:     Not used */
 300         PAD_NC(GPP_F22, NONE),
 301         /* GPP_F23:     SLP_S0#_GATE */
 302         PAD_CFG_GPO(GPP_F23, 1, PLTRST),
 303
 304         /* GPP_H00:     Not used */
 305         PAD_NC(GPP_H00, NONE),
 306         /* GPP_H01:     Not used */
 307         PAD_NC(GPP_H01, NONE),
 308         /* GPP_H02:     Not used */
 309         PAD_NC(GPP_H02, NONE),
 310         /* GPP_H03:     EN_PWR_FP */
 311         PAD_CFG_GPO(GPP_H03, 0, DEEP),
 312         /* GPP_H04:     COEX1 */
 313         PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2),
 314         /* GPP_H05:     COEX2 */
 315         PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2),
 316         /* GPP_H06:     Not used */
 317         PAD_NC(GPP_H06, NONE),
 318         /* GPP_H07:     Not used */
 319         PAD_NC(GPP_H07, NONE),
 320         /* GPP_H08:     UART_0_CRXD_DTXD */
 321         PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 322         /* GPP_H09:     UART_0_CTXD_DRXD */
 323         PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
 324         /* GPP_H10:     Not used */
 325         PAD_NC(GPP_H10, NONE),
 326         /* GPP_H11:     GSC_SOC_INT_ODL */
 327         PAD_CFG_GPI_APIC(GPP_H11, NONE, PLTRST, LEVEL, INVERT),
 328         /* GPP_H13:     CPU_C10_GATE# */
 329         PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
 330         /* GPP_H14:     ISH_I2C_1_SDA */
 331         PAD_CFG_NF(GPP_H14, NONE, DEEP, NF2),
 332         /* GPP_H15:     ISH_I2C_1_SCL */
 333         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF2),
 334         /* GPP_H16:     SOC_AUDIO_STRAP */
 335         PAD_CFG_GPI(GPP_H16, NONE, DEEP),
 336         /* GPP_H17:     FP_RST_1V8_OD# */
 337         PAD_CFG_GPO(GPP_H17, 1, DEEP),
 338         /* GPP_H19:     Not used*/
 339         PAD_NC(GPP_H19, NONE),
 340         /* GPP_H20:     Not used */
 341         PAD_NC(GPP_H20, NONE),
 342         /* GPP_H21:     SOC_I2C_1_SDA */
 343         PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
 344         /* GPP_H22:     SOC_I2C_1_SCL */
 345         PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
 346
 347         /* GPP_S00:     SNDW_3_SCL */
 348         PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
 349         /* GPP_S01:     SNDW_3_SDA */
 350         PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
 351         /* GPP_S02:     SOC_DMIC_CLK0 */
 352         PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
 353         /* GPP_S03:     SOC_DMIC_DATA0 */
 354         PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
 355         /* GPP_S04:     SNDW2_CLK */
 356         PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
 357         /* GPP_S05:     SNDW2_DATA0 */
 358         PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
 359         /* GPP_S06:     SOC_DMIC_CLK1 */
 360         PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
 361         /* GPP_S07:     SOC_DMIC_DATA1 */
 362         PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
 363
 364         /* GPP_V00:     PM_BATLOW# */
 365         PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
 366         /* GPP_V01:     AC_PRESENT */
 367         PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
 368         /* GPP_V02:     LAN_WAKE# */
 369         PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
 370         /* GPP_V03:     PBTN_OUT# */
 371         PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
 372         /* GPP_V04:     PM_SLP_S3# */
 373         PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
 374         /* GPP_V05:     PM_SLP_S4# */
 375         PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
 376         /* GPP_V06:     PM_SLP_A# */
 377         PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
 378         /* GPP_V07:     SUSCLK */
 379         PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
 380         /* GPP_V08:     SLP_WLAN# */
 381         PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
 382         /* GPP_V09:     PM_SLP_S5# */
 383         PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
 384         /* GPP_V10:     Not used  */
 385         PAD_NC(GPP_V10, NONE),
 386         /* GPP_V11:     PM_SLP_LAN# */
 387         PAD_NC(GPP_V11, NONE),
 388         /* GPP_V12:     WAKE# */
 389         PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
 390         /* GPP_V13:     GPP_V13_CATERR_N */
 391         PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
 392         /* GPP_V14:     GPP_V14_FORCEPR_N */
 393         PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
 394         /* GPP_V15:     GPP_V15_THERMTRIP_N */
 395         PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
 396         /* GPP_V16:     VCCST_EN */
 397         PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
 398         /* GPP_V17:     Not used */
 399         PAD_NC(GPP_V17, NONE),
 400 };
 401
 402 /* Early pad configuration in bootblock */
 403 static const struct pad_config early_gpio_table[] = {
 404         /* GPP_H08:     UART_0_CRXD_DTXD */
 405         PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 406         /* GPP_H09:     UART_0_CTXD_DRXD */
 407         PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
 408
 409         /* GPP_H06: SOC_I2C_3_SDA */
 410         PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
 411         /* GPP_H07: SOC_I2C_3_SCL */
 412         PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
 413         /* GPP_D15: GSC_SOC_INT_ODL */
 414         PAD_CFG_GPI_APIC_LOCK(GPP_H11, NONE, LEVEL, INVERT, LOCK_CONFIG),
 415 };
 416
 417 /* Pad configuration in romstage */
 418 static const struct pad_config romstage_gpio_table[] = {
 419         /* GPP_C00:     SOC_SMBCLK */
 420         PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
 421         /* GPP_C01:     SOC_SMBDATA */
 422         PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
 423         /* GPP_F16:     SOC_THC_1_RST# */
 424         PAD_CFG_GPO(GPP_F16, 0, DEEP),
 425         /* GPP_H03:     EN_PWR_FP */
 426         PAD_CFG_GPO(GPP_H03, 0, DEEP),
 427 };
 428
 429 const struct pad_config *variant_gpio_table(size_t *num)
 430 {
 431         *num = ARRAY_SIZE(gpio_table);
 432         return gpio_table;
 433 }
 434
 435 const struct pad_config *variant_early_gpio_table(size_t *num)
 436 {
 437         *num = ARRAY_SIZE(early_gpio_table);
 438         return early_gpio_table;
 439 }
 440
 441 /* Create the stub for romstage gpio, typically use for power sequence */
 442 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 443 {
 444         *num = ARRAY_SIZE(romstage_gpio_table);
 445         return romstage_gpio_table;
 446 }
 447
 448 static const struct cros_gpio cros_gpios[] = {
 449         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
 450         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
 451         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
 452         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
 453 };
 454
 455 DECLARE_CROS_GPIOS(cros_gpios);