src/mainboard/google/fizz/variants/baseboard/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <types.h>
   6 #include <vendorcode/google/chromeos/chromeos.h>
   7
   8 /* Pad configuration in ramstage */
   9 /* Leave eSPI pins untouched from default settings */
  10 static const struct pad_config gpio_table[] = {
  11 /* RCIN# */             PAD_NC(GPP_A0, NONE), /* TP308 */
  12 /* ESPI_IO0 */
  13 /* ESPI_IO1 */
  14 /* ESPI_IO2 */
  15 /* ESPI_IO3 */
  16 /* ESPI_CS# */
  17 /* SERIRQ */            PAD_NC(GPP_A6, NONE), /* TP331 */
  18 /* PIRQA# */            PAD_CFG_GPI_INT(GPP_A7, UP_20K, DEEP,
  19                                         EDGE_SINGLE), /* SD_CDZ */
  20 /* CLKRUN# */           PAD_NC(GPP_A8, NONE), /* TP329 */
  21 /* ESPI_CLK */
  22 /* CLKOUT_LPC1 */       PAD_NC(GPP_A10, NONE), /* TP188 */
  23 /* PME# */              PAD_NC(GPP_A11, NONE), /* TP149 */
  24 /* BM_BUSY# */          PAD_NC(GPP_A12, NONE),
  25 /* SUSWARN# */          PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE,
  26                                                 DEEP), /* eSPI mode */
  27 /* ESPI_RESET# */
  28 /* SUSACK# */           PAD_NC(GPP_A15, NONE), /* TP150 */
  29 /* SD_1P8_SEL */        PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
  30 /* SD_PWR_EN# */        PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
  31 /* ISH_GP0 */           PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */
  32 /* ISH_GP1 */           PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */
  33 /* ISH_GP2 */           PAD_NC(GPP_A20, NONE),
  34 /* ISH_GP3 */           PAD_NC(GPP_A21, NONE),
  35 /* ISH_GP4 */           PAD_NC(GPP_A22, NONE),
  36 /* ISH_GP5 */           PAD_NC(GPP_A23, NONE),
  37
  38 /* CORE_VID0 */         PAD_NC(GPP_B0, NONE), /* TP156 */
  39 /* CORE_VID1 */         PAD_NC(GPP_B1, NONE),
  40 /* VRALERT# */          PAD_NC(GPP_B2, NONE), /* TP152 */
  41 /* CPU_GP2 */           PAD_NC(GPP_B3, NONE),
  42 /* CPU_GP3 */           PAD_NC(GPP_B4, NONE),
  43 /* SRCCLKREQ0# */       PAD_CFG_NF(GPP_B5, NONE, DEEP,
  44                                    NF1), /* CLK_PCIE_LAN_REQ# */
  45 /* SRCCLKREQ1# */       PAD_CFG_NF(GPP_B6, NONE, DEEP,
  46                                    NF1), /* PCIE_CLKREQ_SSD# */
  47 /* SRCCLKREQ2# */       PAD_CFG_NF(GPP_B7, NONE, DEEP,
  48                                    NF1), /* PCIE_CLKREQ_NGFF1# */
  49 /* SRCCLKREQ3# */       PAD_NC(GPP_B8, NONE), /* TP333 */
  50 /* SRCCLKREQ4# */       PAD_NC(GPP_B9, NONE), /* TP139 */
  51 /* SRCCLKREQ5# */       PAD_CFG_NF(GPP_B10, NONE, DEEP,
  52                                    NF1), /* PCIE_CLKREQ_WLAN# */
  53 /* EXT_PWR_GATE# */     PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */
  54 /* SLP_S0# */           PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */
  55 /* PLTRST# */           PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */
  56 /* SPKR */              PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */
  57 /* GSPI0_CS# */         PAD_CFG_NF(GPP_B15, NONE, DEEP,
  58                                    NF1), /* PCH_SPI_H1_3V3_CS_L */
  59 /* GSPI0_CLK */         PAD_CFG_NF(GPP_B16, NONE, DEEP,
  60                                    NF1), /* PCH_SPI_H1_3V3_CLK */
  61 /* GSPI0_MISO */        PAD_CFG_NF(GPP_B17, NONE, DEEP,
  62                                    NF1), /* PCH_SPI_H1_3V3_MISO */
  63 /* GSPI0_MOSI */        PAD_CFG_NF(GPP_B18, NONE, DEEP,
  64                                    NF1), /* PCH_SPI_H1_3V3_MOSI */
  65 /* GSPI1_CS# */         PAD_NC(GPP_B19, NONE), /* TP111 */
  66 /* GSPI1_CLK */         PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, UP_20K,
  67                                                 DEEP), /* VR_DISABLE_L */
  68 /* GSPI1_MISO */        PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, UP_20K,
  69                                                 DEEP), /* HWA_TRST_N */
  70 /* GSPI1_MOSI */        PAD_NC(GPP_B22, NONE), /* GSPI1_MOSI */
  71 /* SML1ALERT# */        PAD_NC(GPP_B23, NONE), /* TP141 */
  72
  73 /* SMBCLK */            PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */
  74 /* SMBDATA */           PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */
  75 /* SMBALERT# */         PAD_NC(GPP_C2, NONE),
  76 /* SML0CLK */           PAD_NC(GPP_C3, NONE),
  77 /* SML0DATA */          PAD_NC(GPP_C4, NONE),
  78 /* SML0ALERT# */        PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
  79 /* SM1CLK */            PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K,
  80                                                 DEEP), /* EC_IN_RW */
  81 /* SM1DATA */           PAD_NC(GPP_C7, NONE), /* TP310 */
  82 /* UART0_RXD */         PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, UP_20K,
  83                                                         DEEP), /* GPIO1 */
  84 /* UART0_TXD */         PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, UP_20K,
  85                                                         DEEP), /* GPIO2 */
  86 /* UART0_RTS# */        PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, UP_20K,
  87                                                 DEEP), /* GPIO3 */
  88 /* UART0_CTS# */        PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, UP_20K,
  89                                                 DEEP), /* GPIO4 */
  90 /* UART1_RXD */         PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE,
  91                                                         DEEP), /* SKU_ID0 */
  92 /* UART1_TXD */         PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE,
  93                                                         DEEP), /* SKU_ID1 */
  94 /* UART1_RTS# */        PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE,
  95                                                 DEEP), /* SKU_ID2 */
  96 /* UART1_CTS# */        PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE,
  97                                                 DEEP), /* SKU_ID3 */
  98 /* I2C0_SDA */          PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
  99 /* I2C0_SCL */          PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
 100 /* I2C1_SDA */          PAD_NC(GPP_C18, NONE),
 101 /* I2C1_SCL */          PAD_NC(GPP_C19, NONE),
 102 /* UART2_RXD */         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
 103 /* UART2_TXD */         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
 104 /* UART2_RTS# */        PAD_NC(GPP_C22, NONE), /* TP309 */
 105 /* UART2_CTS# */        PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,
 106                                     DEEP), /* SCREW_SPI_WP_STATUS */
 107
 108 /* SPI1_CS# */          PAD_NC(GPP_D0, NONE), /* TP259 */
 109 /* SPI1_CLK */          PAD_NC(GPP_D1, NONE), /* TP260 */
 110 /* SPI1_MISO */         PAD_NC(GPP_D2, NONE), /* TP261 */
 111 /* SPI1_MOSI */         PAD_NC(GPP_D3, NONE), /* TP262 */
 112 /* FASHTRIG */          PAD_NC(GPP_D4, NONE), /* TP153 */
 113 /* ISH_I2C0_SDA */      PAD_NC(GPP_D5, NONE),
 114 /* ISH_I2C0_SCL */      PAD_NC(GPP_D6, NONE),
 115 /* ISH_I2C1_SDA */      PAD_NC(GPP_D7, NONE),
 116 /* ISH_I2C1_SCL */      PAD_NC(GPP_D8, NONE),
 117 /* ISH_SPI_CS# */       PAD_CFG_GPI_INT(GPP_D9, NONE,
 118                                         PLTRST, EDGE_SINGLE), /* HP_IRQ_GPIO */
 119 /* ISH_SPI_CLK */       PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE,
 120                                                 DEEP), /* OEM_ID1 */
 121 /* ISH_SPI_MISO */      PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE,
 122                                                 DEEP), /* OEM_ID2 */
 123 /* ISH_SPI_MOSI */      PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE,
 124                                                 DEEP), /* OEM_ID3 */
 125 /* ISH_UART0_RXD */     PAD_NC(GPP_D13, NONE),
 126 /* ISH_UART0_TXD */     PAD_NC(GPP_D14, NONE),
 127 /* ISH_UART0_RTS# */    PAD_NC(GPP_D15, NONE),
 128 /* ISH_UART0_CTS# */    PAD_NC(GPP_D16, NONE),
 129 /* DMIC_CLK1 */         PAD_NC(GPP_D17, NONE),
 130 /* DMIC_DATA1 */        PAD_NC(GPP_D18, NONE),
 131 /* DMIC_CLK0 */         PAD_NC(GPP_D19, NONE), /* TP121 */
 132 /* DMIC_DATA0 */        PAD_NC(GPP_D20, NONE), /* TP122 */
 133 /* SPI1_IO2 */          PAD_NC(GPP_D21, NONE), /* TP257 */
 134 /* SPI1_IO3 */          PAD_NC(GPP_D22, NONE), /* TP258 */
 135 /* I2S_MCLK */          PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */
 136
 137 /* SATAXPCI0 */         PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST, LEVEL,
 138                                          INVERT), /* H1_PCH_INT_ODL */
 139 /* SATAXPCIE1 */        PAD_CFG_NF(GPP_E1, NONE, DEEP,
 140                                    NF1), /* MB_PCIE_SATA#_DET */
 141 /* SATAXPCIE2 */        PAD_CFG_NF(GPP_E2, UP_20K, DEEP,
 142                                    NF1), /* DB_PCIE_SATA#_DET */
 143 /* CPU_GP0 */           PAD_NC(GPP_E3, NONE),
 144 /* SATA_DEVSLP0 */      PAD_NC(GPP_E4, NONE), /* TP103 */
 145 /* SATA_DEVSLP1 */      PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */
 146 /* SATA_DEVSLP2 */      PAD_NC(GPP_E6, NONE), /* DEVSLP2_DB */
 147 /* CPU_GP1 */           PAD_NC(GPP_E7, NONE),
 148 /* SATALED# */          PAD_NC(GPP_E8, NONE), /* TP314 */
 149 /* USB2_OCO# */         PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */
 150 /* USB2_OC1# */         PAD_CFG_NF(GPP_E10, NONE, DEEP,
 151                                         NF1), /* Rear Dual-Stack USB Ports */
 152 /* USB2_OC2# */         PAD_CFG_NF(GPP_E11, NONE, DEEP,
 153                                            NF1), /* Front USB Ports */
 154 /* USB2_OC3# */         PAD_CFG_NF(GPP_E12, NONE, DEEP,
 155                                            NF1), /* Rear Single USB Port */
 156 /* DDPB_HPD0 */         PAD_CFG_NF(GPP_E13, NONE, DEEP,
 157                                            NF1), /* INT_HDMI_HPD */
 158 /* DDPC_HPD1 */         PAD_CFG_NF(GPP_E14, NONE, DEEP,
 159                                            NF1), /* DDI2_HPD */
 160 /* DDPD_HPD2 */         PAD_NC(GPP_E15, NONE), /* TP325 */
 161 /* DDPE_HPD3 */         PAD_NC(GPP_E16, NONE), /* TP326 */
 162 /* EDP_HPD */           PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 163 /* DDPB_CTRLCLK */      PAD_CFG_NF(GPP_E18, NONE, DEEP,
 164                                    NF1), /* HDMI_DDCCLK_SW */
 165 /* DDPB_CTRLDATA */     PAD_CFG_NF(GPP_E19, DN_20K, DEEP,
 166                                    NF1), /* HDMI_DDCCLK_DATA */
 167 /* DDPC_CTRLCLK */      PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */
 168 /* DDPC_CTRLDATA */     PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */
 169 /* DDPD_CTRLCLK */      PAD_NC(GPP_E22, NONE),
 170 /* DDPD_CTRLDATA */     PAD_NC(GPP_E23, NONE),
 171
 172 /* I2S2_SCLK */         PAD_NC(GPP_F0, NONE), /* TP191 */
 173 /* I2S2_SFRM */         PAD_NC(GPP_F1, NONE), /* TP192 */
 174 /* I2S2_TXD */          PAD_NC(GPP_F2, NONE), /* TP190 */
 175 /* I2S2_RXD */          PAD_NC(GPP_F3, NONE), /* TP189 */
 176 /* I2C2_SDA */          PAD_CFG_NF(GPP_F4, NONE, DEEP,
 177                                    NF1), /* PCH_I2C2_H1_3V3_SDA */
 178 /* I2C2_SCL */          PAD_CFG_NF(GPP_F5, NONE, DEEP,
 179                                    NF1), /* PCH_I2C2_H1_3V3_SCL */
 180 /* I2C3_SDA */          PAD_NC(GPP_F6, NONE),
 181 /* I2C3_SCL */          PAD_NC(GPP_F7, NONE),
 182 /* I2C4_SDA */          PAD_NC(GPP_F8, NONE),
 183 /* I2C4_SCL */          PAD_NC(GPP_F9, NONE),
 184 /* I2C5_SDA */          PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP,
 185                                        NF1), /* PCH_I2C2_AUDIO_1V8_SDA */
 186 /* I2C5_SCL */          PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP,
 187                                        NF1), /* PCH_I2C2_AUDIO_1V8_SCL */
 188 /* EMMC_CMD */          PAD_NC(GPP_F12, NONE),
 189 /* EMMC_DATA0 */        PAD_NC(GPP_F13, NONE),
 190 /* EMMC_DATA1 */        PAD_NC(GPP_F14, NONE),
 191 /* EMMC_DATA2 */        PAD_NC(GPP_F15, NONE),
 192 /* EMMC_DATA3 */        PAD_NC(GPP_F16, NONE),
 193 /* EMMC_DATA4 */        PAD_NC(GPP_F17, NONE),
 194 /* EMMC_DATA5 */        PAD_NC(GPP_F18, NONE),
 195 /* EMMC_DATA6 */        PAD_NC(GPP_F19, NONE),
 196 /* EMMC_DATA7 */        PAD_NC(GPP_F20, NONE),
 197 /* EMMC_RCLK */         PAD_NC(GPP_F21, NONE),
 198 /* EMMC_CLK */          PAD_NC(GPP_F22, NONE),
 199 /* RSVD */              PAD_NC(GPP_F23, NONE),
 200
 201 /* SD_CMD */            PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
 202 /* SD_DATA0 */          PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
 203 /* SD_DATA1 */          PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
 204 /* SD_DATA2 */          PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
 205 /* SD_DATA3 */          PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
 206 /* SD_CD# */            PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */
 207 /* SD_CLK */            PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
 208 /* SD_WP */             PAD_NC(GPP_G7, NONE), /* TP292 */
 209
 210 /* BATLOW# */           PAD_NC(GPD0, NONE), /* TP148 */
 211 /* ACPRESENT */         PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */
 212 /* LAN_WAKE# */         PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */
 213 /* PWRBTN# */           PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PCH_PWRBTN# */
 214 /* SLP_S3# */           PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */
 215 /* SLP_S4# */           PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */
 216 /* SLP_A# */            PAD_NC(GPD6, NONE), /* TP147 */
 217 /* RSVD */              PAD_NC(GPD7, NONE),
 218 /* SUSCLK */            PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */
 219 /* SLP_WLAN# */         PAD_NC(GPD9, NONE), /* TP146 */
 220 /* SLP_S5# */           PAD_NC(GPD10, NONE), /* TP143 */
 221 /* LANPHYC */           PAD_NC(GPD11, NONE),
 222 };
 223
 224 /* Early pad configuration in bootblock */
 225 static const struct pad_config early_gpio_table[] = {
 226 /* GSPI0_CS# */         PAD_CFG_NF(GPP_B15, NONE, DEEP,
 227                                    NF1), /* PCH_SPI_H1_3V3_CS_L */
 228 /* GSPI0_CLK */         PAD_CFG_NF(GPP_B16, NONE, DEEP,
 229                                    NF1), /* PCH_SPI_H1_3V3_CLK */
 230 /* GSPI0_MISO */        PAD_CFG_NF(GPP_B17, NONE, DEEP,
 231                                    NF1), /* PCH_SPI_H1_3V3_MISO */
 232 /* GSPI0_MOSI */        PAD_CFG_NF(GPP_B18, NONE, DEEP,
 233                                    NF1), /* PCH_SPI_H1_3V3_MOSI */
 234 /* SATAXPCI0 */         PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST, LEVEL,
 235                                          INVERT), /* H1_PCH_INT_ODL */
 236 /* Ensure UART pins are in native mode for H1. */
 237 /* UART2_RXD */         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
 238 /* UART2_TXD */         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
 239 /* UART2_CTS# */        PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,
 240                                     DEEP), /* SCREW_SPI_WP_STATUS */
 241 /* SATAXPCIE1 */       PAD_CFG_NF(GPP_E1, NONE, DEEP,
 242                                   NF1), /* MB_PCIE_SATA#_DET */
 243 /* SATA_DEVSLP1 */     PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */
 244
 245 /* SM1CLK */            PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K,
 246                                                 DEEP), /* EC_IN_RW */
 247 };
 248
 249 const struct pad_config * __weak variant_gpio_table(size_t *num)
 250 {
 251         *num = ARRAY_SIZE(gpio_table);
 252         return gpio_table;
 253 }
 254
 255 const struct pad_config * __weak
 256         variant_early_gpio_table(size_t *num)
 257 {
 258         *num = ARRAY_SIZE(early_gpio_table);
 259         return early_gpio_table;
 260 }
 261
 262 static const struct cros_gpio cros_gpios[] = {
 263         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
 264         CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
 265 };
 266
 267 DECLARE_WEAK_CROS_GPIOS(cros_gpios);