src/mainboard/google/glados/devicetree.cb

   1 chip soc/intel/skylake
   2
   3         # IGD Displays
   4         register "gfx" = "GMA_STATIC_DISPLAYS(0)"
   5
   6         register "panel_cfg" = "{
   7                 .up_delay_ms            =  200,
   8                 .down_delay_ms          =   50,
   9                 .cycle_delay_ms         =  500,
  10                 .backlight_on_delay_ms  =    1,
  11                 .backlight_off_delay_ms =  200,
  12                 .backlight_pwm_hz       = 1000,
  13         }"
  14
  15         # Enable deep Sx states
  16         register "deep_s3_enable_ac" = "0"
  17         register "deep_s3_enable_dc" = "0"
  18         register "deep_s5_enable_ac" = "1"
  19         register "deep_s5_enable_dc" = "1"
  20         register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
  21
  22         # GPE configuration
  23         # Note that GPE events called out in ASL code rely on this
  24         # route. i.e. If this route changes then the affected GPE
  25         # offset bits also need to be changed.
  26         register "gpe0_dw0" = "GPP_B"
  27         register "gpe0_dw1" = "GPP_D"
  28         register "gpe0_dw2" = "GPP_E"
  29
  30         # Enable DPTF
  31         register "dptf_enable" = "1"
  32
  33         # FSP Configuration
  34         register "DspEnable" = "1"
  35         register "IoBufferOwnership" = "3"
  36         register "ScsEmmcHs400Enabled" = "1"
  37         register "SkipExtGfxScan" = "1"
  38         register "SaGv" = "SaGv_Enabled"
  39         register "PmConfigSlpS3MinAssert" = "2"        # 50ms
  40         register "PmConfigSlpS4MinAssert" = "4"        # 4s
  41         register "PmConfigSlpSusMinAssert" = "3"       # 4s
  42         register "PmConfigSlpAMinAssert" = "3"         # 2s
  43
  44         # Must leave UART0 enabled or SD/eMMC will not work as PCI
  45         register "SerialIoDevMode" = "{
  46                 [PchSerialIoIndexI2C0]  = PchSerialIoPci,
  47                 [PchSerialIoIndexI2C1]  = PchSerialIoPci,
  48                 [PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
  49                 [PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
  50                 [PchSerialIoIndexI2C4]  = PchSerialIoPci,
  51                 [PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
  52                 [PchSerialIoIndexSpi0]  = PchSerialIoDisabled,
  53                 [PchSerialIoIndexSpi1]  = PchSerialIoDisabled,
  54                 [PchSerialIoIndexUart0] = PchSerialIoPci,
  55                 [PchSerialIoIndexUart1] = PchSerialIoDisabled,
  56                 [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
  57         }"
  58
  59         # I2C4 is 1.8V
  60         register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
  61
  62         # PL2 override 25W
  63         register "power_limits_config" = "{
  64                 .tdp_pl2_override = 25,
  65         }"
  66
  67         # Send an extra VR mailbox command for the PS4 exit issue
  68         register "SendVrMbxCmd" = "2"
  69
  70         device domain 0 on
  71                 device ref igpu         on  end
  72                 device ref sa_thermal   on  end
  73                 device ref south_xhci   on  end
  74                 device ref thermal      on  end
  75                 device ref i2c0         on  end
  76                 device ref i2c1         on  end
  77                 device ref heci1        on  end
  78                 device ref uart2        on  end
  79                 device ref i2c4         on  end
  80                 device ref pcie_rp1     on
  81                         register "PcieRpEnable[0]" = "1"
  82                         register "PcieRpClkReqSupport[0]" = "1"
  83                         register "PcieRpClkReqNumber[0]" = "1"
  84                         chip drivers/wifi/generic
  85                                 register "wake" = "GPE0_DW0_16"
  86                                 device pci 00.0 on end
  87                         end
  88                 end
  89                 device ref uart0        on  end
  90                 device ref emmc         on  end
  91                 device ref lpc_espi     on
  92                         # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
  93                         register "gen1_dec" = "0x00fc0801"
  94                         register "gen2_dec" = "0x000c0201"
  95
  96                         chip drivers/pc80/tpm
  97                                 device pnp 0c31.0 on end
  98                         end
  99                         chip ec/google/chromeec
 100                                 device pnp 0c09.0 on end
 101                         end
 102                 end
 103                 device ref hda          on  end
 104                 device ref smbus        on  end
 105                 device ref fast_spi     on  end
 106         end
 107 end