soc/intel/xeon_sp: Allow OS to control LTR and AER
[coreboot2.git] / src / mainboard / google / hatch / chromeos-16MiB.fmd
blob8880a4f9fec762dba2d299d16781a1f5aee57908
1 FLASH@0xff000000 0x1000000 {
2         SI_ALL@0x0 0x400000 {
3                 SI_DESC@0x0 0x1000
4                 SI_ME@0x1000 0x3ff000
5         }
6         SI_BIOS@0x400000 0xc00000 {
7                 RW_SECTION_A@0x0 0x368000 {
8                         VBLOCK_A@0x0 0x10000
9                         FW_MAIN_A(CBFS)@0x10000 0x357fc0
10                         RW_FWID_A@0x367fc0 0x40
11                 }
12                 RW_SECTION_B@0x368000 0x368000 {
13                         VBLOCK_B@0x0 0x10000
14                         FW_MAIN_B(CBFS)@0x10000 0x357fc0
15                         RW_FWID_B@0x367fc0 0x40
16                 }
17                 RW_MISC@0x6D0000 0x30000 {
18                         UNIFIED_MRC_CACHE@0x0 0x20000 {
19                                 RECOVERY_MRC_CACHE@0x0 0x10000
20                                 RW_MRC_CACHE@0x10000 0x10000
21                         }
22                         RW_ELOG(PRESERVE)@0x20000 0x4000
23                         RW_SHARED@0x24000 0x4000 {
24                                 SHARED_DATA@0x0 0x2000
25                                 VBLOCK_DEV@0x2000 0x2000
26                         }
27                         RW_VPD(PRESERVE)@0x28000 0x2000
28                         RW_NVRAM(PRESERVE)@0x2a000 0x6000
29                 }
30                 # RW_LEGACY needs to be minimum of 1MB
31                 RW_LEGACY(CBFS)@0x700000 0x100000
32                 WP_RO@0x800000 0x400000 {
33                         RO_VPD(PRESERVE)@0x0 0x4000
34                         RO_SECTION@0x4000 0x3fc000 {
35                                 FMAP@0x0 0x800
36                                 RO_FRID@0x800 0x40
37                                 RO_FRID_PAD@0x840 0x7c0
38                                 GBB@0x1000 0x3000
39                                 COREBOOT(CBFS)@0x4000 0x3f8000
40                         }
41                 }
42         }