src/mainboard/google/kahlee/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/acpi.h>
   4 #include <console/console.h>
   5 #include <device/device.h>
   6 #include <device/mmio.h>
   7 #include <acpi/acpi.h>
   8 #include <amdblocks/agesawrapper.h>
   9 #include <amdblocks/amd_pci_util.h>
  10 #include <amdblocks/i2c.h>
  11 #include <baseboard/variants.h>
  12 #include <boardid.h>
  13 #include <gpio.h>
  14 #include <smbios.h>
  15 #include <soc/acpi.h>
  16 #include <soc/pci_devs.h>
  17 #include <soc/southbridge.h>
  18 #include <stdio.h>
  19 #include <amdblocks/acpimmio.h>
  20 #include <variant/ec.h>
  21 #include <variant/thermal.h>
  22
  23 /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
  24    accessed via I/O ports 0xc00/0xc01. */
  25 static const struct fch_irq_routing fch_irq_map[] = {
  26         { PIRQ_A,        3,             16 },
  27         { PIRQ_B,        4,             17 },
  28         { PIRQ_C,        5,             18 },
  29         { PIRQ_D,        7,             19 },
  30         { PIRQ_E,       11,             20 },
  31         { PIRQ_F,       PIRQ_NC,        PIRQ_NC },
  32         { PIRQ_G,       PIRQ_NC,        22 },
  33         { PIRQ_H,       PIRQ_NC,        23 },
  34         { PIRQ_SCI,     ACPI_SCI_IRQ,   ACPI_SCI_IRQ },
  35         { PIRQ_SMBUS,   PIRQ_NC,        PIRQ_NC },
  36         { PIRQ_HDA,      3,             16 },
  37         { PIRQ_SD,       3,             16 },
  38         { PIRQ_SDIO,    PIRQ_NC,        PIRQ_NC },
  39         { PIRQ_EHCI,     5,             18 },
  40         { PIRQ_XHCI,     4,             18 },
  41         { PIRQ_SATA,     4,             19 },
  42         { PIRQ_GPIO,     7,              7 },
  43         { PIRQ_I2C0,     3,              3 },
  44         { PIRQ_I2C1,    15,             15 },
  45         { PIRQ_I2C2,     6,              6 },
  46         { PIRQ_I2C3,    14,             14 },
  47         { PIRQ_UART0,   10,             10 },
  48         { PIRQ_UART1,   11,             11 },
  49
  50         /* The MISC registers are not interrupt numbers */
  51         { PIRQ_MISC,    0xfa,   0x00 },
  52         { PIRQ_MISC0,   0xf1,   0x00 },
  53         { PIRQ_MISC1,   0x00,   0x00 },
  54         { PIRQ_MISC2,   0x00,   0x00 },
  55 };
  56
  57 const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
  58 {
  59         *length = ARRAY_SIZE(fch_irq_map);
  60         return fch_irq_map;
  61 }
  62
  63 /*
  64  * This table defines the index into the picr/intr_data tables for each
  65  * device.  Any enabled device and slot that uses hardware interrupts should
  66  * have an entry in this table to define its index into the FCH PCI_INTR
  67  * register 0xC00/0xC01.  This index will define the interrupt that it should
  68  *  use. Putting PIRQ_A into the PIN A index for a device will tell that
  69  * device to use PIC IRQ 10 if it uses PIN A for its hardware INT.
  70  */
  71 static const struct pirq_struct mainboard_pirq_data[] = {
  72         { PCIE0_DEVFN,  { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
  73         { PCIE1_DEVFN,  { PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A } },
  74         { PCIE2_DEVFN,  { PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B } },
  75         { PCIE3_DEVFN,  { PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C } },
  76         { PCIE4_DEVFN,  { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
  77         { HDA0_DEVFN,   { PIRQ_NC, PIRQ_HDA, PIRQ_NC, PIRQ_NC } },
  78         { SD_DEVFN,     { PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  79         { SMBUS_DEVFN,  { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  80         { SATA_DEVFN,   { PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  81         { EHCI1_DEVFN,  { PIRQ_EHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  82         { XHCI_DEVFN,   { PIRQ_XHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  83 };
  84
  85 /* PIRQ Setup */
  86 static void pirq_setup(void)
  87 {
  88         pirq_data_ptr = mainboard_pirq_data;
  89         pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
  90 }
  91
  92 void __weak variant_devtree_update(void)
  93 {
  94         /* Override dev tree settings per board */
  95 }
  96
  97 static void mainboard_init(void *chip_info)
  98 {
  99         int boardid = board_id();
 100         size_t num_gpios;
 101         const struct soc_amd_gpio *gpios;
 102
 103         printk(BIOS_INFO, "Board ID: %d\n", boardid);
 104
 105         mainboard_ec_init();
 106
 107         gpios = variant_gpio_table(&num_gpios);
 108         gpio_configure_pads(gpios, num_gpios);
 109
 110         /* Initialize i2c buses that were not initialized in bootblock */
 111         i2c_soc_init();
 112
 113         /* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */
 114         pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE);
 115
 116         /* Set low-power mode for BayHub eMMC bridge's PCIe clock. */
 117         clrsetbits32(acpimmio_misc + GPP_CLK_CNTRL,
 118                      GPP_CLK2_REQ_MAP_MASK,
 119                      GPP_CLK2_REQ_MAP_CLK_REQ2 <<
 120                      GPP_CLK2_REQ_MAP_SHIFT);
 121
 122         /* Same for the WiFi */
 123         clrsetbits32(acpimmio_misc + GPP_CLK_CNTRL,
 124                      GPP_CLK0_REQ_MAP_MASK,
 125                      GPP_CLK0_REQ_MAP_CLK_REQ0 <<
 126                      GPP_CLK0_REQ_MAP_SHIFT);
 127
 128         variant_devtree_update();
 129 }
 130
 131 /*************************************************
 132  * Dedicated mainboard function
 133  *************************************************/
 134 static void mainboard_enable(struct device *dev)
 135 {
 136         /* Initialize the PIRQ data structures for consumption */
 137         pirq_setup();
 138 }
 139
 140 int mainboard_get_xhci_oc_map(uint16_t *map)
 141 {
 142         return variant_get_xhci_oc_map(map);
 143 }
 144
 145 int mainboard_get_ehci_oc_map(uint16_t *map)
 146 {
 147         return variant_get_ehci_oc_map(map);
 148 }
 149
 150 void mainboard_suspend_resume(void)
 151 {
 152         variant_mainboard_suspend_resume();
 153 }
 154
 155 struct chip_operations mainboard_ops = {
 156         .init = mainboard_init,
 157         .enable_dev = mainboard_enable,
 158 };
 159
 160 /* Variants may override these functions so see definitions in variants/ */
 161 uint8_t __weak variant_board_sku(void)
 162 {
 163         return 0;
 164 }
 165
 166 void __weak variant_mainboard_suspend_resume(void)
 167 {
 168 }
 169
 170 const char *smbios_system_sku(void)
 171 {
 172         static char sku_str[7]; /* sku{0..255} */
 173
 174         snprintf(sku_str, sizeof(sku_str), "sku%d", variant_board_sku());
 175
 176         return sku_str;
 177 }