?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
soc/intel/xeon_sp: Allow OS to control LTR and AER
[coreboot2.git] / src / mainboard / google / octopus / variants / baseboard / devicetree.cb
blob138499c884ad8fc1c1576c885e3cf45acfd2bb49
1 chip soc/intel/apollolake
2
3 register "pcie_rp_clkreq_pin[2]" = "3" # wifi/bt
4 # Disable unused clkreq of PCIe root ports
5 register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
6 register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
7 register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
8 register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
9 register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
10
11 # Set de-emphasis to disabled for PCIE WiFI (Thunderpeak)
12 # as it is required for detection
13 register "pcie_rp_deemphasis_enable[2]" = "0"
14 # Set de-emphasis to default (enabled) for remaining ports
15 register "pcie_rp_deemphasis_enable[0]" = "1"
16 register "pcie_rp_deemphasis_enable[1]" = "1"
17 register "pcie_rp_deemphasis_enable[3]" = "1"
18 register "pcie_rp_deemphasis_enable[4]" = "1"
19 register "pcie_rp_deemphasis_enable[5]" = "1"
20
21 # GPIO for PERST_0 (WLAN_PE_RST)
22 register "prt0_gpio" = "GPIO_164"
23
24 # GPE configuration
25 # Note that GPE events called out in ASL code rely on this
26 # route, i.e., if this route changes then the affected GPE
27 # offset bits also need to be changed. This sets the PMC register
28 # GPE_CFG fields.
29 # DW1 is used by:
30 # - GPIO_63 - H1_PCH_INT_ODL
31 # DW2 is used by:
32 # - GPIO_141 - EC_PCH_WAKE_ODL
33 # - GPIO_142 - TRACKPAD_INT2_1V8_ODL
34 # - GPIO_144 - PEN_EJECT_ODL
35 # DW3 is used by:
36 # - GPIO_117 - LTE_WAKE_ODL
37 # - GPIO_119 - WLAN_PCIE_WAKE_ODL
38 register "gpe0_dw1" = "PMC_GPE_NW_63_32"
39 register "gpe0_dw2" = "PMC_GPE_N_95_64"
40 register "gpe0_dw3" = "PMC_GPE_N_63_32"
41
42 # PL1 override 10 W: Due to error in the energy calculation for
43 # current VR solution. Experiments show that SoC TDP max (6W) can
44 # be reached when RAPL PL1 is set to 10W.
45 # Set RAPL PL2 to 15W.
46 register "power_limits_config" = "{
47 .tdp_pl1_override = 10,
48 .tdp_pl2_override = 15,
49 }"
50
51 # Minimum SLP S3 assertion width 28ms.
52 register "slp_s3_assertion_width_usecs" = "28000"
53
54 # Enable lpss s0ix
55 register "lpss_s0ix_enable" = "true"
56
57 # Enable DPTF
58 register "dptf_enable" = "1"
59
60 # Enable Audio Clock and Power gating
61 register "hdaudio_clk_gate_enable" = "1"
62 register "hdaudio_pwr_gate_enable" = "1"
63 register "hdaudio_bios_config_lockdown" = "1"
64
65 # Intel Common SoC Config
66 #+-------------------+---------------------------+
67 #| Field | Value |
68 #+-------------------+---------------------------+
69 #| GSPI0 | cr50 TPM. Early init is |
70 #| | required to set up a BAR |
71 #| | for TPM communication |
72 #| | before memory is up |
73 #| I2C0 | Digitizer |
74 #| I2C5 | Audio |
75 #| I2C6 | Trackpad |
76 #| I2C7 | Touchscreen |
77 #+-------------------+---------------------------+
78 register "common_soc_config" = "{
79 .gspi[0] = {
80 .speed_mhz = 1,
81 .early_init = 1,
82 },
83 .i2c[0] = {
84 .speed = I2C_SPEED_FAST,
85 .rise_time_ns = 152,
86 .fall_time_ns = 30,
87 },
88 .i2c[5] = {
89 .speed = I2C_SPEED_FAST,
90 .rise_time_ns = 104,
91 .fall_time_ns = 52,
92 },
93 .i2c[6] = {
94 .speed = I2C_SPEED_FAST,
95 .rise_time_ns = 114,
96 .fall_time_ns = 164,
97 .data_hold_time_ns = 350,
98 },
99 .i2c[7] = {
100 .speed = I2C_SPEED_FAST,
101 .rise_time_ns = 76,
102 .fall_time_ns = 164,
103 },
104 }"
105
106 register "pnp_settings" = "PNP_PERF_POWER"
107
108 device domain 0 on
109 device pci 00.0 on end # - Host Bridge
110 device pci 00.1 on end # - DPTF
111 device pci 00.2 off end # - NPK
112 device pci 02.0 on # - Gen
113 register "gfx" = "GMA_DEFAULT_PANEL(0)"
114 end
115 device pci 03.0 off end # - Gaussian Mixture Model (GMM)
116 device pci 0c.0 on
117 chip drivers/wifi/generic
118 register "wake" = "GPE0A_CNVI_PME_STS"
119 device generic 0 on end
120 end
121 end # - CNVi
122 device pci 0d.0 on end # - P2SB
123 device pci 0d.1 on end # - PMC
124 device pci 0d.2 on end # - Fast SPI
125 device pci 0d.3 on end # - Shared SRAM
126 device pci 0e.0 on
127 chip drivers/generic/max98357a
128 register "hid" = ""MX98357A""
129 register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)"
130 register "sdmode_delay" = "5"
131 device generic 0 on end
132 end
133 end # - Audio
134 device pci 0f.0 on end # - Heci1
135 device pci 0f.1 on end # - Heci2
136 device pci 0f.2 on end # - Heci3
137 device pci 11.0 off end # - ISH
138 device pci 12.0 off end # - SATA
139 device pci 13.0 on
140 chip drivers/wifi/generic
141 register "wake" = "GPE0_DW3_11"
142 device pci 00.0 on end
143 end
144 end # - PCIe-A 0 Onboard M2 Slot(Wifi)
145 device pci 13.1 off end # - PCIe-A 1
146 device pci 13.2 off end # - PCIe-A 2
147 device pci 13.3 off end # - PCIe-A 3
148 device pci 14.0 off end # - PCIe-B 0
149 device pci 14.1 off end # - PCIe-B 1
150 device pci 15.0 on
151 chip drivers/usb/acpi
152 register "desc" = ""Root Hub""
153 register "type" = "UPC_TYPE_HUB"
154 device usb 0.0 on
155 chip drivers/usb/acpi
156 register "desc" = ""Left Type-C Port""
157 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
158 register "group" = "ACPI_PLD_GROUP(1, 1)"
159 device usb 2.0 on end
160 end
161 chip drivers/usb/acpi
162 register "desc" = ""Left Type-A Port""
163 register "type" = "UPC_TYPE_A"
164 register "group" = "ACPI_PLD_GROUP(1, 2)"
165 device usb 2.1 on end
166 end
167 chip drivers/usb/acpi
168 register "desc" = ""Bluetooth""
169 register "type" = "UPC_TYPE_INTERNAL"
170 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)"
171 device usb 2.2 on end
172 end
173 chip drivers/usb/acpi
174 register "desc" = ""Right Type-A Port""
175 register "type" = "UPC_TYPE_A"
176 register "group" = "ACPI_PLD_GROUP(2, 2)"
177 device usb 2.3 on end
178 end
179 chip drivers/usb/acpi
180 register "desc" = ""Right Type-C Port""
181 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
182 register "group" = "ACPI_PLD_GROUP(2, 1)"
183 device usb 2.4 on end
184 end
185 chip drivers/usb/acpi
186 register "desc" = ""SDCard""
187 register "type" = "UPC_TYPE_EXPRESSCARD"
188 device usb 2.5 on end
189 end
190 chip drivers/usb/acpi
191 register "desc" = ""User Facing Camera""
192 register "type" = "UPC_TYPE_INTERNAL"
193 device usb 2.6 on end
194 end
195 chip drivers/usb/acpi
196 register "desc" = ""World Facing Camera""
197 register "type" = "UPC_TYPE_INTERNAL"
198 device usb 2.7 on end
199 end
200 chip drivers/usb/acpi
201 register "desc" = ""Bluetooth""
202 register "type" = "UPC_TYPE_INTERNAL"
203 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_109)"
204 device usb 2.8 on end
205 end
206 chip drivers/usb/acpi
207 register "desc" = ""Left Type-C Port""
208 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
209 register "group" = "ACPI_PLD_GROUP(1, 1)"
210 device usb 3.0 on end
211 end
212 chip drivers/usb/acpi
213 register "desc" = ""Left Type-A Port""
214 register "type" = "UPC_TYPE_USB3_A"
215 register "group" = "ACPI_PLD_GROUP(1, 2)"
216 device usb 3.1 on end
217 end
218 chip drivers/usb/acpi
219 register "desc" = ""Right Type-A Port""
220 register "type" = "UPC_TYPE_USB3_A"
221 register "group" = "ACPI_PLD_GROUP(2, 2)"
222 device usb 3.3 on end
223 end
224 chip drivers/usb/acpi
225 register "desc" = ""Right Type-C Port""
226 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
227 register "group" = "ACPI_PLD_GROUP(2, 1)"
228 device usb 3.4 on end
229 end
230 chip drivers/usb/acpi
231 register "desc" = ""SDCard""
232 register "type" = "UPC_TYPE_EXPRESSCARD"
233 device usb 3.5 on end
234 end
235 end
236 end
237 end # - XHCI
238 device pci 15.1 off end # - XDCI
239 device pci 16.0 on end # - I2C 0
240 device pci 16.1 off end # - I2C 1
241 device pci 16.2 off end # - I2C 2
242 device pci 16.3 off end # - I2C 3
243 device pci 17.0 on end # - I2C 4
244 device pci 17.1 on end # - I2C 5
245 device pci 17.2 on end # - I2C 6
246 device pci 17.3 off end # - I2C 7
247 device pci 18.0 on end # - UART 0
248 device pci 18.1 off end # - UART 1
249 device pci 18.2 on end # - UART 2
250 device pci 18.3 off end # - UART 3
251 device pci 19.0 on
252 chip drivers/spi/acpi
253 register "hid" = "ACPI_DT_NAMESPACE_HID"
254 register "compat_string" = ""google,cr50""
255 register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_63_IRQ)"
256 device spi 0 on end
257 end
258 end # - GSPI 0
259 device pci 19.1 off end # - SPI 1
260 device pci 19.2 on end # - SPI 2
261 device pci 1a.0 on end # - PWM
262 device pci 1c.0 on end # - eMMC
263 device pci 1d.0 on end # - UFS
264 device pci 1e.0 off end # - SDIO
265 device pci 1f.0 on
266 chip ec/google/chromeec
267 device pnp 0c09.0 on end
268 end
269 end # - ESPI
270 device pci 1f.1 on end # - SMBUS
271 end
272
273 # FSP provides UPD interface to execute IPC command. PMIC has
274 # I2C_Slave_Address (31:24): 0x5E, Register_Offset (23:16): 0x43,
275 # RegOrValue (15:8): 0x2 and RegAndValue (7:0) 0xF8.
276 # The register is defined as: D[7:3] RSVD, D[2:0] PWROKDELAY.
277 # uint8 RegOrValue, RegAndValue, PmicReadReg
278 # RegOrValue = (UINT8)((pmic_pmc_ipc_ctrl >> 8) & 0xff);
279 # RegAndValue = (UINT8)(pmic_pmc_ipc_ctrl & 0xff);
280 # PmicReadReg &= RegAndValue;
281 # PmicReadReg |= RegOrValue;
282 # PmicReadReg value will be programmed into PMIC D[2:0] PWROKDELAY field
283 # and D[7:3] RSVD will not be impacted.
284
285 # Configure pmic_pmc_ipc_ctrl for PMC to program PMIC PCH_PWROK delay
286 # from 100ms to 10ms.
287 # PWROKDELAY[2:0]: 000=2.5ms, 001=5.0ms, 010=10ms, 011=15ms, 100=20ms,
288 # 101=50ms, 110=75ms, 111=100ms (default)
289 register "pmic_pmc_ipc_ctrl" = "0x5e4302f8"
290
291 # FSP UPD to modify the Integrated Filter (IF) value
292 # Set it to default value: 0x12
293 register "mod_phy_if_value" = "0x12"
294 end
coreboot repo mirror