src/mainboard/google/octopus/variants/baseboard/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/variants.h>
   4 #include <boardid.h>
   5 #include <gpio.h>
   6 #include <soc/meminit.h>
   7 #include <variant/gpio.h>
   8
   9 const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = {
  10         /* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */
  11         .phys[LP4_PHYS_CH0A] = {
  12                 /* DQA[0:7] pins of LPDDR4 module. */
  13                 .dqs[LP4_DQS0] = { 4, 6, 7, 5, 3, 2, 1, 0 },
  14                 /* DQA[8:15] pins of LPDDR4 module. */
  15                 .dqs[LP4_DQS1] = { 12, 15, 13, 8, 9, 10, 11, 14 },
  16                 /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
  17                 .dqs[LP4_DQS2] = { 17, 18, 19, 16, 23, 20, 21, 22 },
  18                 /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
  19                 .dqs[LP4_DQS3] = { 30, 31, 25, 27, 26, 29, 28, 24 },
  20         },
  21         .phys[LP4_PHYS_CH0B] = {
  22                 /* DQA[0:7] pins of LPDDR4 module. */
  23                 .dqs[LP4_DQS0] = { 1, 3, 2, 0, 5, 4, 6, 7 },
  24                 /* DQA[8:15] pins of LPDDR4 module. */
  25                 .dqs[LP4_DQS1] = { 15, 14, 13, 12, 8, 9, 11, 10 },
  26                 /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
  27                 .dqs[LP4_DQS2] = { 20, 21, 22, 16, 23, 17, 18, 19 },
  28                 /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
  29                 .dqs[LP4_DQS3] = { 30, 26, 24, 25, 28, 29, 31, 27 },
  30         },
  31         .phys[LP4_PHYS_CH1A] = {
  32                 /* DQA[0:7] pins of LPDDR4 module. */
  33                 .dqs[LP4_DQS0] = { 15, 14, 13, 12, 8, 9, 10, 11 },
  34                 /* DQA[8:15] pins of LPDDR4 module. */
  35                 .dqs[LP4_DQS1] = { 7, 6, 5, 0, 4, 2, 1, 3 },
  36                 /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
  37                 .dqs[LP4_DQS2] = { 20, 21, 23, 22, 19, 17, 18, 16 },
  38                 /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
  39                 .dqs[LP4_DQS3] = { 24, 27, 26, 30, 25, 31, 28, 29 },
  40         },
  41         .phys[LP4_PHYS_CH1B] = {
  42                 /* DQA[0:7] pins of LPDDR4 module. */
  43                 .dqs[LP4_DQS0] = { 0, 4, 7, 1, 6, 5, 3, 2 },
  44                 /* DQA[8:15] pins of LPDDR4 module. */
  45                 .dqs[LP4_DQS1] = { 11, 12, 13, 15, 10, 9, 8, 14 },
  46                 /* DQB[0:7] pins of LPDDR4 module with offset of 16. */
  47                 .dqs[LP4_DQS2] = { 19, 21, 17, 16, 22, 23, 18, 20 },
  48                 /* DQB[7:15] pins of LPDDR4 module with offset of 16. */
  49                 .dqs[LP4_DQS3] = { 30, 26, 25, 24, 31, 29, 28, 27 },
  50         },
  51 };
  52
  53 static const struct lpddr4_sku non_cbi_skus[] = {
  54         /*
  55          * K4F6E304HB-MGCJ - both logical channels While the parts
  56          * are listed at 16Gb there are 2 ranks per channel so indicate
  57          * the density as 8Gb per rank.
  58          */
  59         [0] = {
  60                 .speed = LP4_SPEED_2400,
  61                 .ch0_rank_density = LP4_8Gb_DENSITY,
  62                 .ch1_rank_density = LP4_8Gb_DENSITY,
  63                 .ch0_dual_rank = 1,
  64                 .ch1_dual_rank = 1,
  65                 .part_num = "K4F6E304HB-MGCJ",
  66         },
  67         /* K4F8E304HB-MGCJ - both logical channels  */
  68         [1] = {
  69                 .speed = LP4_SPEED_2400,
  70                 .ch0_rank_density = LP4_8Gb_DENSITY,
  71                 .ch1_rank_density = LP4_8Gb_DENSITY,
  72                 .part_num = "K4F8E304HB-MGCJ",
  73         },
  74         /*
  75          * MT53B512M32D2NP-062WT:C - both logical channels. While the parts
  76          * are listed at 16Gb there are 2 ranks per channel so indicate
  77          * the density as 8Gb per rank.
  78          */
  79         [2] = {
  80                 .speed = LP4_SPEED_2400,
  81                 .ch0_rank_density = LP4_8Gb_DENSITY,
  82                 .ch1_rank_density = LP4_8Gb_DENSITY,
  83                 .ch0_dual_rank = 1,
  84                 .ch1_dual_rank = 1,
  85                 .part_num = "MT53B512M32D2NP",
  86         },
  87         /* MT53B256M32D1NP-062 WT:C - both logical channels */
  88         [3] = {
  89                 .speed = LP4_SPEED_2400,
  90                 .ch0_rank_density = LP4_8Gb_DENSITY,
  91                 .ch1_rank_density = LP4_8Gb_DENSITY,
  92                 .part_num = "MT53B256M32D1NP",
  93         },
  94         /*
  95          * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts
  96          * are listed at 16Gb there are 2 ranks per channel so indicate the
  97          * density as 8Gb per rank.
  98          */
  99         [4] = {
 100                 .speed = LP4_SPEED_2400,
 101                 .ch0_rank_density = LP4_8Gb_DENSITY,
 102                 .ch1_rank_density = LP4_8Gb_DENSITY,
 103                 .ch0_dual_rank = 1,
 104                 .ch1_dual_rank = 1,
 105                 .part_num = "H9HCNNNBPUMLHR",
 106         },
 107         /* H9HCNNN8KUMLHR-NLE - both logical channels */
 108         [5] = {
 109                 .speed = LP4_SPEED_2400,
 110                 .ch0_rank_density = LP4_8Gb_DENSITY,
 111                 .ch1_rank_density = LP4_8Gb_DENSITY,
 112                 .part_num = "H9HCNNN8KUMLHR",
 113         },
 114         /* K4F6E3S4HM-MGCJ - both logical channels */
 115         [6] = {
 116                 .speed = LP4_SPEED_2400,
 117                 .ch0_rank_density = LP4_16Gb_DENSITY,
 118                 .ch1_rank_density = LP4_16Gb_DENSITY,
 119                 .part_num = "K4F6E3S4HM-MGCJ",
 120         },
 121         /* MT53E512M32D2NP-046 - both logical channels */
 122         [7] = {
 123                 .speed = LP4_SPEED_2400,
 124                 .ch0_rank_density = LP4_16Gb_DENSITY,
 125                 .ch1_rank_density = LP4_16Gb_DENSITY,
 126                 .part_num = "MT53E512M32D2NP",
 127         },
 128 };
 129
 130 static const struct lpddr4_cfg non_cbi_lp4cfg = {
 131         .skus = non_cbi_skus,
 132         .num_skus = ARRAY_SIZE(non_cbi_skus),
 133         .swizzle_config = &baseboard_lpddr4_swizzle,
 134 };
 135
 136 static const struct lpddr4_sku cbi_skus[] = {
 137         /* Dual Channel Config 4GiB System Capacity */
 138         [0] = {
 139                 .speed = LP4_SPEED_2400,
 140                 .ch0_rank_density = LP4_8Gb_DENSITY,
 141                 .ch1_rank_density = LP4_8Gb_DENSITY,
 142         },
 143         /* Dual Channel Config 8GiB System Capacity */
 144         [1] = {
 145                 .speed = LP4_SPEED_2400,
 146                 .ch0_rank_density = LP4_16Gb_DENSITY,
 147                 .ch1_rank_density = LP4_16Gb_DENSITY,
 148         },
 149         /* Dual Channel Config 8GiB System Capacity */
 150         [2] = {
 151                 .speed = LP4_SPEED_2400,
 152                 .ch0_rank_density = LP4_8Gb_DENSITY,
 153                 .ch1_rank_density = LP4_8Gb_DENSITY,
 154                 .ch0_dual_rank = 1,
 155                 .ch1_dual_rank = 1,
 156         },
 157         /* Single Channel Configs 4GiB System Capacity Ch0 populated. */
 158         [3] = {
 159                 .speed = LP4_SPEED_2400,
 160                 .ch0_rank_density = LP4_16Gb_DENSITY,
 161         },
 162         /* Single Channel Configs 4GiB System Capacity Ch0 populated. */
 163         [4] = {
 164                 .speed = LP4_SPEED_2400,
 165                 .ch0_rank_density = LP4_8Gb_DENSITY,
 166                 .ch0_dual_rank = 1,
 167         },
 168         /* Dual Channel / Dual Rank Config 4GiB System Capacity */
 169         [5] = {
 170                 .speed = LP4_SPEED_2400,
 171                 .ch0_rank_density = LP4_4Gb_DENSITY,
 172                 .ch1_rank_density = LP4_4Gb_DENSITY,
 173                 .ch0_dual_rank = 1,
 174                 .ch1_dual_rank = 1,
 175         },
 176         /* Dual Channel Config 6GiB System Capacity */
 177         [7] = {
 178                 .speed = LP4_SPEED_2400,
 179                 .ch0_rank_density = LP4_12Gb_DENSITY,
 180                 .ch1_rank_density = LP4_12Gb_DENSITY,
 181         },
 182 };
 183
 184 static const struct lpddr4_cfg cbi_lp4cfg = {
 185         .skus = cbi_skus,
 186         .num_skus = ARRAY_SIZE(cbi_skus),
 187         .swizzle_config = &baseboard_lpddr4_swizzle,
 188 };
 189
 190 const struct lpddr4_cfg *__weak variant_lpddr4_config(void)
 191 {
 192         if (CONFIG(DRAM_PART_NUM_NOT_ALWAYS_IN_CBI)) {
 193                 /* Fall back non cbi memory config. */
 194                 if ((int)board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN)
 195                         return &non_cbi_lp4cfg;
 196         }
 197
 198         return &cbi_lp4cfg;
 199 }
 200
 201 size_t __weak variant_memory_sku(void)
 202 {
 203         gpio_t pads[] = {
 204                 [3] = MEM_CONFIG3, [2] = MEM_CONFIG2,
 205                 [1] = MEM_CONFIG1, [0] = MEM_CONFIG0,
 206         };
 207
 208         return gpio_base2_value(pads, ARRAY_SIZE(pads));
 209 }