soc/intel/xeon_sp: Allow OS to control LTR and AER
[coreboot2.git] / src / mainboard / google / octopus / variants / phaser / Makefile.mk
blobeda39ac58d7344c9ecec444d5c38827bfbda3316
1 ## SPDX-License-Identifier: GPL-2.0-only
3 bootblock-y += gpio.c
5 romstage-y += gpio.c
6 romstage-y += memory.c
8 ramstage-y += variant.c
9 ramstage-y += gpio.c
10 ramstage-y += mainboard.c