src/mainboard/google/puff/variants/baseboard/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/variants.h>
   4 #include <bootmode.h>
   5 #include <chip.h>
   6 #include <console/console.h>
   7 #include <delay.h>
   8 #include <device/device.h>
   9 #include <device/pci_ids.h>
  10 #include <device/pci_ops.h>
  11 #include <ec/google/chromeec/ec.h>
  12 #include <gpio.h>
  13 #include <intelblocks/power_limit.h>
  14 #include <soc/pci_devs.h>
  15 #include <static.h>
  16 #include <timer.h>
  17
  18 #define GPIO_HDMI_HPD           GPP_E13
  19 #define GPIO_DP_HPD             GPP_E14
  20
  21 /* TODO: This can be moved to common directory */
  22 static void wait_for_hpd(gpio_t gpio, long timeout)
  23 {
  24         struct stopwatch sw;
  25
  26         printk(BIOS_INFO, "Waiting for HPD\n");
  27         stopwatch_init_msecs_expire(&sw, timeout);
  28         while (!gpio_get(gpio)) {
  29                 if (stopwatch_expired(&sw)) {
  30                         printk(BIOS_WARNING,
  31                                "HPD not ready after %ldms. Abort.\n", timeout);
  32                         return;
  33                 }
  34                 mdelay(200);
  35         }
  36         printk(BIOS_INFO, "HPD ready after %lld ms\n",
  37                stopwatch_duration_msecs(&sw));
  38 }
  39
  40 /*
  41  * For type-C chargers, set PL2 to 97% of max power to account for
  42  * cable loss and FET Rdson loss in the path from the source.
  43  */
  44 #define SET_PSYSPL2(w)               (97 * (w) / 100)
  45 #define PUFF_U22_PL2                 (35)
  46 #define PUFF_U62_U42_PL2             (51)
  47 #define PUFF_CELERON_PENTIUM_PSYSPL2 (65)
  48 #define PUFF_CORE_CPU_PSYSPL2        (90)
  49 #define PUFF_MAX_TIME_WINDOW         6
  50 #define PUFF_MIN_DUTYCYCLE           4
  51
  52 /*
  53  * mainboard_set_power_limits
  54  *
  55  * Set Pl2 and SysPl2 values based on detected charger.
  56  * Values are defined below but we use U22 value for all SKUs for now.
  57  * definitions:
  58  * x = no value entered. Use default value in parenthesis.
  59  *     will set 0 to anything that shouldn't be set.
  60  * n = max value of power adapter.
  61  * +-------------+-----+---------+-----------+-------+
  62  * | sku_id      | PL2 | PsysPL2 |  PsysPL3  |  PL4  |
  63  * +-------------+-----+---------+-----------+-------+
  64  * | i7 U42      |  51 |   90    | x(.85PL4) | x(82) |
  65  * | i3 U22      |  35 |   65    | x(.85PL4) | x(51) |
  66  * +-------------+-----+---------+-----------+-------+
  67  * For USB C charger:
  68  * +-------------+-----------------+---------+---------+-------+
  69  * | Max Power(W)|       PL2       | PsysPL2 | PsysPL3 |  PL4  |
  70  * +-------------+-----+-----------+---------+---------+-------+
  71  * | n           | min(0.97n, PL2) |  0.97n  |  0.97n  | 0.97n |
  72  * +-------------+-----+-----------+---------+---------+-------+
  73  */
  74
  75 /*
  76  * Psys_pmax considerations
  77  *
  78  * Given the hardware design in puff, the serial shunt resistor is 0.01ohm.
  79  * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A
  80  * instead of real system power. The equation is shown below:
  81  * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k)
  82  * Hence, Iinput (Amps) = 9.6A
  83  * Since there is no voltage information from PSYS, different voltage input
  84  * would map to different Psys_pmax settings:
  85  * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W
  86  * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W
  87  * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W
  88  */
  89 #define PSYS_IMAX    9600
  90 #define BJ_VOLTS_MV  19000
  91
  92 static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
  93 {
  94         enum usb_chg_type type;
  95         u32 watts;
  96         u16 volts_mv, current_ma;
  97         u32 psyspl2 = PUFF_CELERON_PENTIUM_PSYSPL2; // default BJ value
  98         u32 pl2 = PUFF_U22_PL2; // default PL2 for U22
  99         int rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv);
 100
 101         struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 102         u16 mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
 103         dev = pcidev_path_on_root(SA_DEVFN_IGD);
 104         u16 igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
 105
 106         /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/
 107         conf->tdp_psyspl3 = 0;
 108         conf->tdp_pl4 = 0;
 109
 110         if (rv == 0 && type == USB_CHG_TYPE_PD) {
 111                 /* Detected USB-PD.  Base on max value of adapter */
 112                 watts = ((u32)current_ma * volts_mv) / 1000000;
 113                 /* set psyspl2 to 90% of adapter rating */
 114                 psyspl2 = SET_PSYSPL2(watts);
 115
 116                 /* Limit PL2 if the adapter is with lower capability */
 117                 if (mch_id == PCI_DID_INTEL_CML_ULT ||
 118                         mch_id == PCI_DID_INTEL_CML_ULT_6_2)
 119                         pl2 = (psyspl2 > PUFF_U62_U42_PL2) ? PUFF_U62_U42_PL2 : psyspl2;
 120                 else
 121                         pl2 = (psyspl2 > PUFF_U22_PL2) ? PUFF_U22_PL2 : psyspl2;
 122
 123                 conf->tdp_psyspl3 = psyspl2;
 124                 /* set max possible time window */
 125                 conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW;
 126                 /* set minimum duty cycle */
 127                 conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE;
 128                 /* No data about an arbitrary Type-C adapter, set pl4 conservatively. */
 129                 conf->tdp_pl4 = psyspl2;
 130         } else {
 131                 /*
 132                  * Input type is barrel jack, from the SKU matrix:
 133                  * 1. i3/i5/i7 SKUs use 90W BJ
 134                  * 2. Celeron and Pentium use 65W BJ (default)
 135                  */
 136                 volts_mv = BJ_VOLTS_MV;
 137                 /* Use IGD ID to check if CPU is Core SKUs */
 138                 if (igd_id != PCI_DID_INTEL_CML_GT1_ULT_1 &&
 139                         igd_id != PCI_DID_INTEL_CML_GT2_ULT_5) {
 140                         psyspl2 = PUFF_CORE_CPU_PSYSPL2;
 141                         if (mch_id == PCI_DID_INTEL_CML_ULT ||
 142                                 mch_id == PCI_DID_INTEL_CML_ULT_6_2)
 143                                 pl2 = PUFF_U62_U42_PL2;
 144                 }
 145         }
 146         /* voltage unit is milliVolts and current is in milliAmps */
 147         conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000);
 148
 149         conf->tdp_pl2_override = pl2;
 150         conf->tdp_psyspl2 = psyspl2;
 151 }
 152
 153 void variant_ramstage_init(void)
 154 {
 155         static const long display_timeout_ms = 3000;
 156         struct soc_power_limits_config *soc_config;
 157         config_t *conf = config_of_soc();
 158
 159         /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */
 160         gpio_input(GPIO_HDMI_HPD);
 161         gpio_input(GPIO_DP_HPD);
 162         if (display_init_required()
 163                 && !gpio_get(GPIO_HDMI_HPD)
 164                 && !gpio_get(GPIO_DP_HPD)) {
 165                 /* This has to be done before FSP-S runs. */
 166                 if (google_chromeec_wait_for_displayport(display_timeout_ms))
 167                         wait_for_hpd(GPIO_DP_HPD, display_timeout_ms);
 168         }
 169         /* Psys_pmax needs to be setup before FSP-S */
 170         soc_config = &conf->power_limits_config;
 171         mainboard_set_power_limits(soc_config);
 172 }