soc/intel/xeon_sp: Allow OS to control LTR and AER
[coreboot2.git] / src / mainboard / google / rauru / bootblock.c
blob6e0a4eea1625082cb6d8a04c1481b29cdc1b9f87
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <bootblock_common.h>
4 #include <gpio.h>
5 #include <soc/gpio.h>
6 #include <soc/i2c.h>
7 #include <soc/pcie.h>
8 #include <soc/spi.h>
10 #include "gpio.h"
12 static void usb3_hub_reset(void)
14 gpio_output(GPIO(USB_RST), 1);
17 void bootblock_mainboard_init(void)
19 if (CONFIG(PCI))
20 mtk_pcie_pre_init();
22 mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST_PLUS);
23 mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
24 mtk_snfc_init();
25 usb3_hub_reset();
26 setup_chromeos_gpios();
27 gpio_eint_configure(GPIO_GSC_AP_INT_ODL, IRQ_TYPE_EDGE_RISING);