src/mainboard/google/reef/variants/coral/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <baseboard/gpio.h>
   5 #include <baseboard/variants.h>
   6 #include <types.h>
   7 #include <vendorcode/google/chromeos/chromeos.h>
   8
   9 /*
  10  * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
  11  * table found in EDS vol 1, but some pins aren't grouped functionally in
  12  * the table so those were moved for more logical grouping.
  13  */
  14 static const struct pad_config gpio_table[] = {
  15         /* PCIE_WAKE[0:3]_N */
  16         PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE), /* WLAN */
  17         PAD_CFG_GPI(GPIO_206, UP_20K, DEEP),     /* Unused */
  18         PAD_CFG_GPI(GPIO_207, UP_20K, DEEP),     /* Unused */
  19         PAD_CFG_GPI(GPIO_208, UP_20K, DEEP),     /* Unused */
  20
  21         /* EMMC interface */
  22         PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */
  23         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D0 */
  24         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D1 */
  25         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D2 */
  26         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D3 */
  27         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_161, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D4 */
  28         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D5 */
  29         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D6 */
  30         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_164, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_D7 */
  31         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_CMD */
  32         PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */
  33
  34         /* SDIO -- unused. */
  35         PAD_CFG_GPI(GPIO_166, UP_20K, DEEP),     /* SDIO_CLK */
  36         PAD_CFG_GPI(GPIO_167, UP_20K, DEEP),     /* SDIO_D0 */
  37         /* Configure SDIO to enable power gating */
  38         PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1),        /* SDIO_D1 */
  39         PAD_CFG_GPI(GPIO_169, UP_20K, DEEP),     /* SDIO_D2 */
  40         PAD_CFG_GPI(GPIO_170, UP_20K, DEEP),     /* SDIO_D3 */
  41         PAD_CFG_GPI(GPIO_171, UP_20K, DEEP),     /* SDIO_CMD */
  42
  43         /* SDCARD */
  44         /* Pull down clock by 20K */
  45         PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */
  46         PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */
  47         PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */
  48         PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */
  49         PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */
  50         /* Card detect is active LOW with external pull up. */
  51         PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1), /* SDCARD_CD_N */
  52         PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */
  53         /* CLK feedback, internal signal, needs 20K pull down */
  54         PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */
  55         /* No h/w write proect for uSD cards, pull down by 20K */
  56         PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1), /* SDCARD_LVL_WP */
  57         /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */
  58         PAD_CFG_GPO(GPIO_183, 0, DEEP),          /* SDIO_PWR_DOWN_N */
  59
  60         /* SMBus -- unused. */
  61         PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP),   /* SMB_ALERT _N */
  62         PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP),      /* SMB_CLK */
  63         PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP),     /* SMB_DATA */
  64
  65         /*
  66          * LPC
  67          * Note: It's unconfirmed if this redundancy to the bootblock table is necessary.
  68          */
  69         PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */
  70         PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */
  71         PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP),  /* LPC_CLKOUT1 -- unused */
  72         PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),  /* LPC_AD0 */
  73         PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),  /* LPC_AD1 */
  74         PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),  /* LPC_AD2 */
  75         PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),  /* LPC_AD3 */
  76         PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */
  77         PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), /* LPC_FRAME_N */
  78
  79         /* I2C0 - Audio */
  80         PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1), /* LPSS_I2C0_SDA */
  81         PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1), /* LPSS_I2C0_SCL */
  82
  83         /* I2C1 - NFC with external pulls */
  84         PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1), /* LPSS_I2C1_SDA */
  85         PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1), /* LPSS_I2C1_SCL */
  86
  87         /* I2C2 - TPM  */
  88         PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */
  89         PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */
  90
  91         /* I2C3 - touch */
  92         PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1), /* LPSS_I2C3_SDA */
  93         PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1), /* LPSS_I2C3_SCL */
  94
  95         /* I2C4 - trackpad */
  96         /* LPSS_I2C4_SDA */
  97         PAD_CFG_NF_IOSSTATE(GPIO_132, UP_2K, DEEP, NF1, HIZCRx1),
  98         /* LPSS_I2C4_SCL */
  99         PAD_CFG_NF_IOSSTATE(GPIO_133, UP_2K, DEEP, NF1, HIZCRx1),
 100
 101         /* I2C5 -- pen with external pulls  */
 102         PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1), /* LPSS_I2C5_SDA */
 103         PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1), /* LPSS_I2C5_SCL */
 104
 105         /* I2C6-7 -- unused. */
 106         PAD_CFG_GPI(GPIO_136, UP_20K, DEEP),     /* LPSS_I2C6_SDA */
 107         PAD_CFG_GPI(GPIO_137, UP_20K, DEEP),     /* LPSS_I2C6_SCL */
 108         PAD_CFG_GPI(GPIO_138, UP_20K, DEEP),     /* LPSS_I2C7_SDA */
 109         PAD_CFG_GPI(GPIO_139, UP_20K, DEEP),     /* LPSS_I2C7_SCL */
 110
 111         /* Audio Amp - I2S6 */
 112         PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2), /* ISH_GPIO_0 - I2S6_BCLK */
 113         PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2), /* ISH_GPIO_1 - I2S6_WS_SYNC */
 114         PAD_CFG_GPI(GPIO_148, UP_20K, DEEP),     /* ISH_GPIO_2 - unused */
 115         PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2), /* ISH_GPIO_3 - I2S6_SDO */
 116
 117         /* NFC Reset */
 118         PAD_CFG_GPO(GPIO_150, 1, DEEP),          /* ISH_GPIO_4 */
 119
 120         PAD_CFG_GPI(GPIO_151, UP_20K, DEEP),     /* ISH_GPIO_5 - unused */
 121
 122         /* Touch enable */
 123         PAD_CFG_GPO(GPIO_152, 1, DEEP),          /* ISH_GPIO_6 */
 124
 125         PAD_CFG_GPI(GPIO_153, UP_20K, DEEP),     /* ISH_GPIO_7 - unused */
 126         PAD_CFG_GPI(GPIO_154, UP_20K, DEEP),     /* ISH_GPIO_8 - unused */
 127         PAD_CFG_GPI(GPIO_155, UP_20K, DEEP),     /* ISH_GPIO_9 - unused */
 128
 129         /* PCIE_CLKREQ[0:3]_N */
 130         PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1),   /* WLAN with external pull */
 131         PAD_CFG_GPI(GPIO_210, UP_20K, DEEP),     /* unused */
 132         PAD_CFG_GPI(GPIO_211, UP_20K, DEEP),     /* unused */
 133         PAD_CFG_GPI(GPIO_212, UP_20K, DEEP),     /* unused */
 134
 135         /* OSC_CLK_OUT_[0:4] -- unused */
 136         PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP),
 137         PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP),
 138         PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP),
 139         PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP),
 140         PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP),
 141
 142         /* PMU Signals */
 143         PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP), /* PMU_AC_PRESENT - unused */
 144         PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */
 145         PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */
 146         PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), /* PMU_PWRBTN_N */
 147         PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */
 148         PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), /* PMU_SLP_S0_N */
 149         PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */
 150         PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */
 151         PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */
 152         PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP),        /* EN_PP3300_EMMC */
 153         PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1), /* SUS_STAT_N */
 154         PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1), /* SUSPWRDNACK */
 155
 156         /* DDI[0:1] SDA and SCL -- unused */
 157         PAD_CFG_GPI(GPIO_187, UP_20K, DEEP),     /* HV_DDI0_DDC_SDA */
 158         PAD_CFG_GPI(GPIO_188, UP_20K, DEEP),     /* HV_DDI0_DDC_SCL */
 159         PAD_CFG_GPI(GPIO_189, UP_20K, DEEP),     /* HV_DDI1_DDC_SDA */
 160         PAD_CFG_GPI(GPIO_190, UP_20K, DEEP),     /* HV_DDI1_DDC_SCL */
 161
 162         /* MIPI I2C -- unused */
 163         PAD_CFG_GPI(GPIO_191, UP_20K, DEEP),     /* MIPI_I2C_SDA */
 164         PAD_CFG_GPI(GPIO_192, UP_20K, DEEP),     /* MIPI_I2C_SCL */
 165
 166         /* Panel 0 control */
 167         PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1), /* PNL0_VDDEN */
 168         PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1), /* PNL0_BKLTEN */
 169         PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1), /* PNL0_BKLTCTL */
 170
 171         /* Panel 1 control -- unused */
 172         PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1), /* PNL1_VDDEN */
 173         PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1), /* PNL1_BKLTEN */
 174         PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1), /* PNL1_BKLTCTL */
 175
 176         /* Hot plug detect. */
 177         PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */
 178         PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */
 179
 180         /* MDSI signals -- unused */
 181         PAD_CFG_GPI(GPIO_201, UP_20K, DEEP),     /* MDSI_A_TE */
 182         PAD_CFG_GPI(GPIO_202, UP_20K, DEEP),     /* MDSI_A_TE */
 183
 184         /* USB overcurrent pins. */
 185         PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1), /* USB_OC0_N */
 186         PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1), /* USB_OC1_N */
 187
 188         /* PMC SPI -- almost entirely unused */
 189         PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP),
 190         PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2), /* HV_DDI2_HPD -- EDP HPD */
 191         PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP),
 192         PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP),
 193         PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP),
 194         PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP),
 195
 196         /* PMIC Signals Unused signals related to an old PMIC interface */
 197         PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE), /* PMIC_RESET_B */
 198         PAD_CFG_GPI(GPIO_213, NONE, DEEP),       /* unused external pull */
 199         PAD_CFG_GPI(GPIO_214, UP_20K, DEEP),     /* unused */
 200         PAD_CFG_GPI(GPIO_215, UP_20K, DEEP),     /* unused */
 201         PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), /* THERMTRIP_N */
 202         PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP),   /* unused */
 203         PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), /* PROCHOT_N */
 204         PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1), /* PMIC_I2C_SCL */
 205         PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1), /* PMIC_I2C_SDA */
 206
 207         /* I2S1 -- largely unused */
 208         PAD_CFG_GPI(GPIO_74, UP_20K, DEEP),     /* I2S1_MCLK */
 209         PAD_CFG_GPI(GPIO_75, UP_20K, DEEP),     /* I2S1_BCLK -- PCH_WP */
 210         PAD_CFG_GPO(GPIO_76, 0, DEEP),          /* I2S1_WS_SYNC -- SPK_PA_EN */
 211         PAD_CFG_GPI(GPIO_77, UP_20K, DEEP),     /* I2S1_SDI */
 212         PAD_CFG_GPO(GPIO_78, 1, DEEP),          /* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */
 213
 214         /* DMIC or I2S4 */
 215         /* AVS_DMIC_CLK_A1 */
 216         PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, IGNORE),
 217         PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1), /* AVS_DMIC_CLK_B1 */
 218         PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_1 */
 219         PAD_CFG_GPI(GPIO_82, DN_20K, DEEP),      /* unused -- strap */
 220         PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_2 */
 221
 222         /* I2S2 -- Headset amp */
 223         PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1),  /* AVS_I2S2_MCLK */
 224         PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1),  /* AVS_I2S2_BCLK */
 225         PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1),  /* AVS_I2S2_SW_SYNC */
 226         PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1),  /* AVS_I2S2_SDI */
 227         PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1),  /* AVS_I2S2_SDO */
 228
 229         /* I2S3 -- largely unused. */
 230         PAD_CFG_GPI(GPIO_89, UP_20K, DEEP),      /* unused */
 231         PAD_CFG_GPI(GPIO_90, UP_20K, DEEP),      /* GPS_HOST_WAKE */
 232         PAD_CFG_GPO(GPIO_91, 1, DEEP),           /* GPS_EN */
 233         PAD_CFG_GPI(GPIO_92, DN_20K, DEEP),      /* unused -- strap */
 234
 235         /* Fast SPI */
 236         PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE),        /* FST_SPI_CS0_B */
 237         PAD_CFG_GPI(GPIO_98, UP_20K, DEEP),                             /* FST_SPI_CS1_B -- unused */
 238         PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE),        /* FST_SPI_MOSI_IO0 */
 239         PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE),       /* FST_SPI_MISO_IO1 */
 240         PAD_CFG_GPI(GPIO_101, NONE, DEEP),                              /* FST_IO2 -- MEM_CONFIG0 */
 241         PAD_CFG_GPI(GPIO_102, NONE, DEEP),                              /* FST_IO3 -- MEM_CONFIG1 */
 242         PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE),       /* FST_SPI_CLK */
 243         PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE), /* FST_SPI_CLK_FB */
 244         PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE),       /* FST_SPI_CS2_N */
 245
 246         /* SIO_SPI_0 - Used for FP */
 247         PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1),                        /* SIO_SPI_0_CLK */
 248         PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1),                        /* SIO_SPI_0_FS0 */
 249         PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1),                        /* SIO_SPI_0_RXD */
 250         PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1),                        /* SIO_SPI_0_TXD */
 251
 252         /* SIO_SPI_1 -- largely unused */
 253         PAD_CFG_GPI(GPIO_111, UP_20K, DEEP),     /* SIO_SPI_1_CLK */
 254         PAD_CFG_GPI(GPIO_112, UP_20K, DEEP),     /* SIO_SPI_1_FS0 */
 255         PAD_CFG_GPI(GPIO_113, UP_20K, DEEP),     /* SIO_SPI_1_FS1 */
 256         /* Headset interrupt */
 257         PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP), /* SIO_SPI_1_RXD */
 258         PAD_CFG_GPI(GPIO_117, UP_20K, DEEP),     /* SIO_SPI_1_TXD */
 259
 260         /* SIO_SPI_2 -- unused */
 261         PAD_CFG_GPI(GPIO_118, UP_20K, DEEP),     /* SIO_SPI_2_CLK */
 262         PAD_CFG_GPI(GPIO_119, UP_20K, DEEP),     /* SIO_SPI_2_FS0 */
 263         PAD_CFG_GPI(GPIO_120, UP_20K, DEEP),     /* SIO_SPI_2_FS1 */
 264         PAD_CFG_GPI(GPIO_121, UP_20K, DEEP),     /* SIO_SPI_2_FS2 */
 265         /* WLAN_PE_RST - default to deasserted. */
 266         PAD_CFG_GPO(GPIO_122, 0, DEEP),          /* SIO_SPI_2_RXD */
 267         PAD_CFG_GPI(GPIO_123, UP_20K, DEEP),     /* SIO_SPI_2_TXD */
 268
 269         /* Debug tracing. */
 270         PAD_CFG_GPI(GPIO_0, UP_20K, DEEP),
 271         PAD_CFG_GPI(GPIO_1, UP_20K, DEEP),
 272         PAD_CFG_GPI(GPIO_2, UP_20K, DEEP),
 273         PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL),       /* FP_INT */
 274         PAD_CFG_GPI(GPIO_4, UP_20K, DEEP),
 275         PAD_CFG_GPI(GPIO_5, UP_20K, DEEP),
 276         PAD_CFG_GPI(GPIO_6, UP_20K, DEEP),
 277         PAD_CFG_GPI(GPIO_7, UP_20K, DEEP),
 278         PAD_CFG_GPI(GPIO_8, UP_20K, DEEP),
 279
 280         PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP), /* dTPM IRQ */
 281         PAD_CFG_GPI(GPIO_10, DN_20K, DEEP),      /* Board phase enforcement */
 282         PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI  */
 283         PAD_CFG_GPI(GPIO_12, UP_20K, DEEP),      /* unused */
 284         PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP), /* PEN_INT_ODL */
 285         PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP), /* FP_INT */
 286         PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE),   /* TRACKPAD_INT_1V8_ODL */
 287         PAD_CFG_GPI(GPIO_16, UP_20K, DEEP),      /* unused */
 288         PAD_CFG_GPI(GPIO_17, UP_20K, DEEP),      /* 1 vs 4 DMIC config */
 289         PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP), /* Trackpad IRQ */
 290         PAD_CFG_GPI(GPIO_19, UP_20K, DEEP),      /* unused */
 291         PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP), /* NFC IRQ */
 292         PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP), /* Touch IRQ */
 293         PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE), /* EC wake */
 294         PAD_CFG_GPI(GPIO_23, UP_20K, DEEP),      /* unused */
 295         PAD_CFG_GPI(GPIO_24, NONE, DEEP),        /* PEN_PDCT_ODL */
 296         PAD_CFG_GPI(GPIO_25, UP_20K, DEEP),      /* unused */
 297         PAD_CFG_GPI(GPIO_26, UP_20K, DEEP),      /* unused */
 298         PAD_CFG_GPI(GPIO_27, UP_20K, DEEP),      /* unused */
 299         PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */
 300         PAD_CFG_GPO(GPIO_29, 1, DEEP),           /* FP reset */
 301         PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP), /* KB IRQ */
 302         PAD_CFG_GPO(GPIO_31, 0, DEEP),           /* NFC FW DL */
 303         PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5),    /* SUS_CLK2 */
 304         PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP), /* PMIC IRQ */
 305         PAD_CFG_GPI(GPIO_34, UP_20K, DEEP),      /* unused */
 306         PAD_CFG_GPO(GPIO_35, 0, DEEP),           /* PEN_RESET - active high */
 307         PAD_CFG_GPO(GPIO_36, 0, DEEP),           /* touch reset */
 308         PAD_CFG_GPI(GPIO_37, UP_20K, DEEP),      /* unused */
 309
 310         /* LPSS_UART[0:2] */
 311         PAD_CFG_GPI(GPIO_38, NONE, DEEP),        /* LPSS_UART0_RXD - MEM_CONFIG2*/
 312         /* Next 2 are straps. */
 313         PAD_CFG_GPI(GPIO_39, DN_20K, DEEP),      /* LPSS_UART0_TXD - unused */
 314         PAD_CFG_GPI(GPIO_40, DN_20K, DEEP),      /* LPSS_UART0_RTS - unused */
 315         PAD_CFG_GPI(GPIO_41, NONE, DEEP),        /* LPSS_UART0_CTS - EC_IN_RW */
 316         PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1),  /* LPSS_UART1_RXD */
 317         PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1),  /* LPSS_UART1_TXD */
 318         PAD_CFG_GPO(GPIO_44, 1, DEEP),   /* GPS_RST_ODL */
 319         PAD_CFG_GPI(GPIO_45, NONE, DEEP),        /* LPSS_UART1_CTS - MEM_CONFIG3 */
 320         PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1),  /* LPSS_UART2_RXD */
 321         PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */
 322         PAD_CFG_GPI(GPIO_48, UP_20K, DEEP),      /* LPSS_UART2_RTS - unused */
 323         PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE), /* LPSS_UART2_CTS - EC_SMI_L */
 324
 325         /* Camera interface -- completely unused. */
 326         PAD_CFG_GPI(GPIO_62, UP_20K, DEEP),      /* GP_CAMERASB00 */
 327         PAD_CFG_GPI(GPIO_63, UP_20K, DEEP),      /* GP_CAMERASB01 */
 328         PAD_CFG_GPI(GPIO_64, UP_20K, DEEP),      /* GP_CAMERASB02 */
 329         PAD_CFG_GPI(GPIO_65, UP_20K, DEEP),      /* GP_CAMERASB03 */
 330         PAD_CFG_GPI(GPIO_66, UP_20K, DEEP),      /* GP_CAMERASB04 */
 331         PAD_CFG_GPI(GPIO_67, UP_20K, DEEP),      /* GP_CAMERASB05 */
 332         PAD_CFG_GPI(GPIO_68, UP_20K, DEEP),      /* GP_CAMERASB06 */
 333         PAD_CFG_GPI(GPIO_69, UP_20K, DEEP),      /* GP_CAMERASB07 */
 334         PAD_CFG_GPI(GPIO_70, UP_20K, DEEP),      /* GP_CAMERASB08 */
 335         PAD_CFG_GPI(GPIO_71, UP_20K, DEEP),      /* GP_CAMERASB09 */
 336         PAD_CFG_GPI(GPIO_72, UP_20K, DEEP),      /* GP_CAMERASB10 */
 337         PAD_CFG_GPI(GPIO_73, UP_20K, DEEP),      /* GP_CAMERASB11 */
 338 };
 339
 340 const struct pad_config *variant_gpio_table(size_t *num)
 341 {
 342         *num = ARRAY_SIZE(gpio_table);
 343         return gpio_table;
 344 }
 345
 346 /* GPIOs needed prior to ramstage. */
 347 static const struct pad_config early_gpio_table[] = {
 348         /* LPC */
 349         PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */
 350         PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */
 351         PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP),  /* LPC_CLKOUT1 -- unused */
 352         PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),  /* LPC_AD0 */
 353         PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),  /* LPC_AD1 */
 354         PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),  /* LPC_AD2 */
 355         PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),  /* LPC_AD3 */
 356         PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */
 357         PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), /* LPC_FRAME_N */
 358
 359         /* UART */
 360         PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1),  /* LPSS_UART2_RXD */
 361         PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */
 362
 363         PAD_CFG_GPI(GPIO_75, UP_20K, DEEP),      /* I2S1_BCLK -- PCH_WP */
 364
 365         /* I2C2 - TPM  */
 366         PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */
 367         PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */
 368         PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */
 369
 370         /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */
 371         PAD_CFG_GPO(GPIO_122, 0, DEEP),          /* SIO_SPI_2_RXD */
 372
 373         PAD_CFG_GPI(GPIO_41, NONE, DEEP),        /* LPSS_UART0_CTS - EC_IN_RW */
 374 };
 375
 376 const struct pad_config *variant_early_gpio_table(size_t *num)
 377 {
 378         *num = ARRAY_SIZE(early_gpio_table);
 379         return early_gpio_table;
 380 }
 381
 382 /* Default GPIO settings before entering sleep. */
 383 static const struct pad_config default_sleep_gpio_table[] = {
 384         PAD_CFG_GPO(GPIO_150, 0, DEEP),         /* NFC_RESET_ODL */
 385         PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP),      /* NFC_INT_L */
 386 };
 387
 388 /* GPIO settings before entering S5, which are same as default_sleep_gpio_table
 389  * but also turn off EN_PP3300_DX_LTE_SOC. */
 390 static const struct pad_config s5_sleep_gpio_table[] = {
 391         PAD_CFG_GPO(GPIO_150, 0, DEEP),         /* NFC_RESET_ODL */
 392         PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP),      /* NFC_INT_L */
 393         PAD_CFG_GPO(GPIO_78, 0, DEEP),          /* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */
 394 };
 395
 396 const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num)
 397 {
 398         if (slp_typ == ACPI_S5) {
 399                 *num = ARRAY_SIZE(s5_sleep_gpio_table);
 400                 return s5_sleep_gpio_table;
 401         }
 402         *num = ARRAY_SIZE(default_sleep_gpio_table);
 403         return default_sleep_gpio_table;
 404 }
 405
 406 static const struct cros_gpio cros_gpios[] = {
 407         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME),
 408         CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME),
 409         CROS_GPIO_PE_AH(PAD_N(GPIO_SHIP_MODE), GPIO_COMM_N_NAME),
 410 };
 411
 412 DECLARE_CROS_GPIOS(cros_gpios);