src/mainboard/google/rex/variants/karis/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <types.h>
   6 #include <soc/gpio.h>
   7 #include <vendorcode/google/chromeos/chromeos.h>
   8
   9 /* Pad configuration in ramstage */
  10 static const struct pad_config gpio_table[] = {
  11         /* GPP_A00 : GPP_A00 ==> ESPI_SOC_IO0_R */
  12         PAD_CFG_NF_IOSSTATE(GPP_A00, UP_20K, DEEP, NF1, IGNORE),
  13         /* GPP_A01 : GPP_A01 ==> ESPI_SOC_IO1_R */
  14         PAD_CFG_NF_IOSSTATE(GPP_A01, UP_20K, DEEP, NF1, IGNORE),
  15         /* GPP_A02 : GPP_A02 ==> ESPI_SOC_IO2_R */
  16         PAD_CFG_NF_IOSSTATE(GPP_A02, UP_20K, DEEP, NF1, IGNORE),
  17         /* GPP_A03 : GPP_A03 ==> ESPI_SOC_IO3_R */
  18         PAD_CFG_NF_IOSSTATE(GPP_A03, UP_20K, DEEP, NF1, IGNORE),
  19         /* GPP_A04 : GPP_A04 ==> ESPI_SOC_CS0_L */
  20         PAD_CFG_NF_IOSSTATE(GPP_A04, UP_20K, DEEP, NF1, IGNORE),
  21         /* GPP_A05 : GPP_A05 ==> ESPI_SOC_CLK_R */
  22         PAD_CFG_NF_IOSSTATE(GPP_A05, UP_20K, DEEP, NF1, IGNORE),
  23         /* GPP_A06 : GPP_A06 ==> ESPI_SOC_RESET_L */
  24         PAD_CFG_NF_IOSSTATE(GPP_A06, UP_20K, DEEP, NF1, IGNORE),
  25         /* GPP_A11 : [] ==> EN_UCAM_SENR_PWR */
  26         PAD_CFG_GPO(GPP_A11, 0, DEEP),
  27         /* GPP_A12 : [] ==> EN_UCAM_PWR, test point. */
  28         PAD_NC(GPP_A12, NONE),
  29         /* GPP_A13 : Not connected */
  30         PAD_NC(GPP_A13, NONE),
  31         /* GPP_A14 : NC pad. */
  32         PAD_NC(GPP_A14, NONE),
  33         /* GPP_A15 : NC pad. */
  34         PAD_NC(GPP_A15, NONE),
  35         /* GPP_A16 : GPP_A16 ==> ESPI_SOC_ALERT_L */
  36         PAD_CFG_NF_IOSSTATE(GPP_A16, UP_20K, DEEP, NF1, IGNORE),
  37         /* GPP_A17 : [] ==> EC_SOC_INT_ODL */
  38         PAD_CFG_GPI_APIC_LOCK(GPP_A17, NONE, LEVEL, INVERT, LOCK_CONFIG),
  39
  40         /* GPP_A18 : [] ==> CAM_PSW_L */
  41         PAD_NC(GPP_A18, NONE),
  42         /* GPP_A19 : [] ==> EN_PP3300_SSD */
  43         PAD_CFG_GPO(GPP_A19, 1, DEEP),
  44         /* GPP_A20 : [] ==> SSD_PERST_L */
  45         PAD_CFG_GPO_LOCK(GPP_A20, 1, LOCK_CONFIG),
  46         /* GPP_A21 : [] ==> PMCALERT */
  47         PAD_NC(GPP_A21, NONE),
  48
  49         /* GPP_B00 : [] ==> TCHPAD_INT_ODL_LS */
  50         PAD_CFG_GPI_IRQ_WAKE(GPP_B00, NONE, PWROK, LEVEL, INVERT),
  51         /* GPP_B01 : [] ==> BT_DISABLE_L */
  52         PAD_CFG_GPO(GPP_B01, 1, DEEP),
  53         /* GPP_B02 : net NC is not present in the given design */
  54         PAD_NC(GPP_B02, NONE),
  55         /* GPP_B03 : net NC is not present in the given design */
  56         PAD_NC(GPP_B03, NONE),
  57         /* GPP_B04 : GPP_B04_STRAP ==> Component NC */
  58         PAD_NC(GPP_B04, NONE),
  59         /* GPP_B05 : [] ==> SPKR_INT_L_R */
  60         PAD_CFG_GPI(GPP_B05, NONE, DEEP),
  61         /* GPP_B06 : [] ==> HP_INT_L_R */
  62         PAD_CFG_GPI_INT(GPP_B06, NONE, PLTRST, EDGE_BOTH),
  63         /* GPP_B07 : [] ==> CAM_DET_L */
  64         PAD_CFG_GPI_INT_LOCK(GPP_B07, NONE, EDGE_BOTH, LOCK_CONFIG),
  65         /* GPP_B08 : net NC is not present in the given design */
  66         PAD_NC(GPP_B08, NONE),
  67         /* GPP_B09 : [] ==> EN_FCAM_PWR */
  68         PAD_CFG_GPO(GPP_B09, 0, DEEP),
  69         /* GPP_B10 : [] ==> WIFI_DISABLE_L */
  70         PAD_CFG_GPO(GPP_B10, 1, DEEP),
  71         /* GPP_B11 : [] ==> EN_FP_PWR */
  72         PAD_CFG_GPO_LOCK(GPP_B11, 0, LOCK_CONFIG),
  73         /* GPP_B12 : [] ==> SLP_SO_R_L */
  74         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  75         /* GPP_B13 : [] ==> PLT_RST_L */
  76         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  77         /* GPP_B14 : GPP_B14_STRAP ==> Component NC */
  78         PAD_NC(GPP_B14, NONE),
  79         /* GPP_B15 : [] ==> USB_OC3# */
  80         PAD_CFG_NF_LOCK(GPP_B15, NONE, NF1, LOCK_CONFIG),
  81         /* GPP_B16 : [] ==> SOC_HDMI_HPD_L */
  82         PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
  83         /* GPP_B17 : NC pad. */
  84         PAD_NC(GPP_B17, NONE),
  85         /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */
  86         PAD_CFG_NF_LOCK(GPP_B18, NONE, NF2, LOCK_CONFIG),
  87         /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */
  88         PAD_CFG_NF_LOCK(GPP_B19, NONE, NF2, LOCK_CONFIG),
  89         /* GPP_B20 : [] ==> SOC_I2C_MISC_SDA */
  90         PAD_CFG_NF_LOCK(GPP_B20, NONE, NF2, LOCK_CONFIG),
  91         /* GPP_B21 : [] ==> SOC_I2C_MISC_SCL */
  92         PAD_CFG_NF_LOCK(GPP_B21, NONE, NF2, LOCK_CONFIG),
  93         /* GPP_B22 : [] ==> USB4_RT_FORCE_PWR */
  94         PAD_CFG_GPO(GPP_B22, 0, DEEP),
  95         /* GPP_B23 : NC pad. */
  96         PAD_NC(GPP_B23, NONE),
  97
  98         /* GPP_C00 : [] ==> EN_TCHSCR_PWR */
  99         PAD_CFG_GPO(GPP_C00, 1, DEEP),
 100         /* GPP_C01 : [] ==>  SOC_TCHSCR_RST_R_L */
 101         PAD_CFG_GPO(GPP_C01, 1, DEEP),
 102         /* GPP_C02 : SOC_TCHSCR_SPI_INT_STRAP ==> Component NC */
 103         PAD_NC(GPP_C02, NONE),
 104         /* GPP_C03 : [] ==> Test pad. */
 105         PAD_NC(GPP_C03, NONE),
 106         /* GPP_C04 : net NC. */
 107         PAD_NC(GPP_C04, NONE),
 108         /* GPP_C05 : [] ==> WWAN_PERST_L_STRAP */
 109         PAD_NC(GPP_C05, NONE),
 110         /* GPP_C06 : [] ==> SOC_TCHSCR_RPT_EN */
 111         PAD_CFG_GPO(GPP_C06, 0, DEEP),
 112         /* GPP_C07 : [] ==> SOC_TCHSCR_INT */
 113         PAD_CFG_GPI_APIC(GPP_C07, NONE, PLTRST, LEVEL, NONE),
 114         /* GPP_C08 : [] ==> SOCHOT_ODL */
 115         PAD_CFG_NF(GPP_C08, NONE, DEEP, NF2),
 116         /* GPP_C09 : net NC is not present in the given design */
 117         PAD_NC(GPP_C09, NONE),
 118         /* GPP_C10 : net NC is not present in the given design */
 119         PAD_NC(GPP_C10, NONE),
 120         /* GPP_C11 : Not Connected */
 121         PAD_NC(GPP_C11, NONE),
 122         /* GPP_C12 : NC pad. */
 123         PAD_NC(GPP_C12, NONE),
 124         /* GPP_C13 : Not connected */
 125         PAD_NC(GPP_C13, NONE),
 126         /* GPP_C15 : [] ==> WWAN_DPR_SAR_ODL */
 127         PAD_NC(GPP_C15, NONE),
 128         /* GPP_C16 : [] ==> USB_C0_LSX_TX */
 129         PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 130         /* GPP_C17 : [] ==> USB_C0_LSX_RX */
 131         PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
 132         /* GPP_C18 : Not Connected. */
 133         PAD_NC(GPP_C18, NONE),
 134         /* GPP_C19 : Not Connected. */
 135         PAD_NC(GPP_C19, NONE),
 136         /* GPP_C20 : [] ==> USB_C1_LSX_TX */
 137         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 138         /* GPP_C21 : [] ==> USB_C1_LSX_RX */
 139         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 140         /* GPP_C22 : [] ==> SOC_FP_BOOT0 */
 141         PAD_CFG_GPO_LOCK(GPP_C22, 0, LOCK_CONFIG),
 142         /* GPP_C23 : [] ==> FP_RST_ODL */
 143         PAD_CFG_GPO_LOCK(GPP_C23, 0, LOCK_CONFIG),
 144
 145         /* GPP_D00 : Not connected. */
 146         PAD_NC(GPP_D00, NONE),
 147         /* GPP_D01 : Not Connected */
 148         PAD_NC(GPP_D01, NONE),
 149         /* GPP_D04 : Not Connected. */
 150         PAD_NC(GPP_D04, NONE),
 151         /* GPP_D05 : net NC.  Test pad. */
 152         PAD_NC(GPP_D05, NONE),
 153         /* GPP_D06 : net NC.  Test pad.*/
 154         PAD_NC(GPP_D06, NONE),
 155         /* GPP_D07 : [] ==> FPMCU_UWB_MUX_SEL, test pad. */
 156         PAD_NC(GPP_D07, NONE),
 157         /* GPP_D08 : [] ==> CAM_NC_RES */
 158         PAD_CFG_GPO(GPP_D08, 1, DEEP),
 159         /* GPP_D09 : [] ==> I2S_MCLK_R */
 160         PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2),
 161         /* GPP_D10 : [] ==> I2S_SPKR_SCLK_R */
 162         PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
 163         /* GPP_D11 : [] ==> I2S_SPKR_SFRM_R */
 164         PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
 165         /* GPP_D12 : [] ==> I2S_SOC_TX_SPKR_RX_R_STRAP */
 166         PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF2),
 167         /* GPP_D13 : [] ==> I2S_SOC_RX_SPKR_TX */
 168         PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2),
 169         /* GPP_D14 : [] ==> I2S_HP_SCLK_R */
 170         PAD_CFG_NF(GPP_D14, NONE, DEEP, NF2),
 171         /* GPP_D15 : [] ==> I2S_HP_SFRM_R */
 172         PAD_CFG_NF(GPP_D15, NONE, DEEP, NF2),
 173         /* GPP_D16 : [] ==> I2S_SOC_TX_HP_RX_R */
 174         PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2),
 175         /* GPP_D17 : [] ==> I2S_SOC_RX_HP_TX */
 176         PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2),
 177         /* GPP_D18 : net NC is not present in the given design */
 178         PAD_NC(GPP_D18, NONE),
 179         /* GPP_D19 : [] ==> EC_SOC_REC_SWITCH_ODL */
 180         PAD_CFG_GPI_LOCK(GPP_D19, NONE, LOCK_CONFIG),
 181         /* GPP_D20 : [] ==> SSD_CLKREQ_ODL */
 182         PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
 183         /* GPP_D21 : [] ==> WLAN_CLKREQ_ODLl */
 184         PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2),
 185         /* GPP_D22 : net NC is not present in the given design */
 186         PAD_NC(GPP_D22, NONE),
 187         /* GPP_D23 : net NC is not present in the given design */
 188         PAD_NC(GPP_D23, NONE),
 189
 190         /* GPP_E00 : NC net. */
 191         PAD_NC(GPP_E00, NONE),
 192         /* GPP_E01 : MEM_STRAP_2 ==> Component NC */
 193         PAD_CFG_GPI_LOCK(GPP_E01, NONE, LOCK_CONFIG),
 194         /* GPP_E02 : MEM_STRAP_1 ==> Component NC */
 195         PAD_CFG_GPI_LOCK(GPP_E02, NONE, LOCK_CONFIG),
 196         /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */
 197         PAD_CFG_GPI_APIC_LOCK(GPP_E03, NONE, LEVEL, INVERT, LOCK_CONFIG),
 198         /* GPP_E04 : [] ==> SOC_PEN_DETECT */
 199         PAD_CFG_GPI_GPIO_DRIVER(GPP_E04, NONE, PLTRST),
 200         /* GPP_E05 : [] ==> USB_A0_RT_RST_ODL */
 201         PAD_CFG_GPO(GPP_E05, 1, DEEP),
 202         /* GPP_E06 : GPP_E06_STRAP ==> Component NC */
 203         PAD_NC(GPP_E06, NONE),
 204         /* GPP_E07 : NC pad. */
 205         PAD_NC(GPP_E07, NONE),
 206         /* GPP_E08 : NC net. */
 207         PAD_NC(GPP_E08, NONE),
 208         /* GPP_E09 : SOC_PEN_DETECT */
 209         PAD_CFG_GPI_SCI_LOCK(GPP_E09, NONE, EDGE_SINGLE, NONE, LOCK_CONFIG),
 210         /* GPP_E10 : [] ==> SOC_FPMCU_INT_L */
 211         PAD_CFG_GPI_IRQ_WAKE(GPP_E10, NONE, PWROK, LEVEL, INVERT),
 212         /* GPP_E11 : [] ==> MEM_STRAP_0 */
 213         PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG),
 214         /* GPP_E12 : [] ==> MEM_STRAP_3 */
 215         PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG),
 216         /* GPP_E13 :  [] ==> MEM_CH_SEL */
 217         PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
 218         /* GPP_E14 : [] ==> SOC_EDP_HPD_L */
 219         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 220         /* GPP_E15 : net NC is not present in the given design */
 221         PAD_NC(GPP_E15, NONE),
 222         /* GPP_E16 : net NC.  Test pad. */
 223         PAD_NC(GPP_E16, NONE),
 224         /* GPP_E17 : net NC is not present in the given design */
 225         PAD_NC(GPP_E17, NONE),
 226         /* GPP_E22 : [] ==> EN_PP3300_WLAN */
 227         PAD_CFG_GPO(GPP_E22, 1, DEEP),
 228
 229         /* GPP_F00 :  [] ==> CNV_BRI_DT_R */
 230         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
 231         /* GPP_F01 :  [] ==> CNV_BRI_RSP */
 232         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, UP_20K, DEEP, NF1),
 233         /* GPP_F02 :  [] ==> CNV_RGI_DT_Rl */
 234         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
 235         /* GPP_F03 :  [] ==> CNV_RGI_RSP */
 236         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, UP_20K, DEEP, NF1),
 237         /* GPP_F04 :  [] ==> CNV_RF_RST_L */
 238         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
 239         /* GPP_F05 :  [] ==> CNV_CLKREQ */
 240         PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
 241         /* GPP_F06 :  [] ==> WWAN_WLAN_COEX3 */
 242         PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
 243         /* GPP_F07 :  [] ==> UCAM_MCLK_R */
 244         PAD_NC(GPP_F07, NONE),
 245         /* GPP_F08 : [] ==> WLAN_PERST_L */
 246         PAD_CFG_GPO(GPP_F08, 1, DEEP),
 247         /* GPP_F09 : [] ==> WLAN_PE_WAKE_ODL */
 248         PAD_CFG_GPI_IRQ_WAKE(GPP_F09, NONE, PLTRST, LEVEL, INVERT),
 249         /* GPP_F10 : NC pad. */
 250         PAD_NC(GPP_F10, NONE),
 251         /* GPP_F11 : GSP1_SOC_CLK_R */
 252         PAD_CFG_NF(GPP_F11, NONE, DEEP, NF5),
 253         /* GPP_F12 : GSPI1_SOC_DO_FPMCU_DI_R */
 254         PAD_CFG_NF(GPP_F12, NONE, DEEP, NF5),
 255         /* GPP_F13 : GSPI1_SOC_DI_FPMCU_DO_LS_R */
 256         PAD_CFG_NF(GPP_F13, NONE, DEEP, NF5),
 257         /* GPP_F14 : net NC. */
 258         PAD_NC(GPP_F14, NONE),
 259         /* GPP_F15 : net NC. */
 260         PAD_NC(GPP_F15, NONE),
 261         /* GPP_F16 : net NC. */
 262         PAD_NC(GPP_F16, NONE),
 263         /* GPP_F17 : [] ==> GSPI1_SOC_CS_L */
 264         PAD_CFG_NF(GPP_F17, NONE, DEEP, NF5),
 265         /* GPP_F18 : net NC. */
 266         PAD_NC(GPP_F18, NONE),
 267         /* GPP_F19 : [] ==> GPP_F19_STRAP */
 268         PAD_NC(GPP_F19, NONE),
 269         /* GPP_F20 : [] ==> GPP_F20_STRAP */
 270         PAD_NC(GPP_F20, NONE),
 271         /* GPP_F21 : [] ==> SPI_SOC_CS_UWB_L_STRAP */
 272         PAD_NC(GPP_F21, NONE),
 273         /* GPP_F22 : net NC is not present in the given design */
 274         PAD_NC(GPP_F22, NONE),
 275         /* GPP_F23 : net NC is not present in the given design */
 276         PAD_NC(GPP_F23, NONE),
 277
 278         /* GPP_H00 : SPI_SOC_CLK_UWB_STRAP_R ==> Component NC */
 279         PAD_NC(GPP_H00, NONE),
 280         /* GPP_H01 : SPI_SOC_DO_UWB_DI_STRAP_R ==> Component NC */
 281         PAD_NC(GPP_H01, NONE),
 282         /* GPP_H02 : SPI_SOC_DI_UWB_DO_STRAP ==> Component NC */
 283         PAD_NC(GPP_H02, NONE),
 284         /* GPP_H04 : [] ==> WWAN_WLAN_COEX1 */
 285         PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2),
 286         /* GPP_H05 : [] ==> WWAN_WLAN_COEX2 */
 287         PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2),
 288         /* GPP_H06 : [] ==> SOC_I2C_TCHPAD_SDA */
 289         PAD_CFG_NF_LOCK(GPP_H06, NONE, NF1, LOCK_CONFIG),
 290         /* GPP_H07 : [] ==> SOC_I2C_TCHPAD_SCL */
 291         PAD_CFG_NF_LOCK(GPP_H07, NONE, NF1, LOCK_CONFIG),
 292         /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */
 293         PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 294         /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */
 295         PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
 296         /* GPP_H10 : [] ==> SOC_WP_OD */
 297         PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG),
 298         /* GPP_H11 : net NC is not present in the given design */
 299         PAD_NC(GPP_H11, NONE),
 300         /* GPP_H13 : [] ==> CPU_C10_GATE_L */
 301         PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
 302         /* GPP_H14 : [] ==> SLP_S0_GATE_R */
 303         PAD_CFG_GPO(GPP_H14, 1, PLTRST),
 304         /* GPP_H15 : [] ==> CAM_SEN_EN */
 305         PAD_CFG_GPO_LOCK(GPP_H15, 0, LOCK_CONFIG),
 306         /* GPP_H16 : [] ==> DDIB_HDMI_CTRLCLK*/
 307         PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
 308         /* GPP_H17 : [] ==> DDIB_HDMI_CTRLDATA */
 309         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 310         /* GPP_H19 : [] ==> SOC_I2C_AUD_WFC_SDA */
 311         PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
 312         /* GPP_H20 : [] ==> SOC_I2C_AUD_WFC_SCL */
 313         PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
 314         /* GPP_H21 : [] ==>  SOC_I2C_TCHSCR_SDA */
 315         PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
 316         /* GPP_H22 : [] ==>  SOC_I2C_TCHSCR_SCL */
 317         PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
 318
 319         /* GPP_S00 :  [] ==> SDW_HP_CLK_WLAN_PCM_CLK  */
 320         PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
 321         /* GPP_S01 :  [] ==> SDW_HP_DATA_WLAN_PCM_SYNC */
 322         PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
 323         /* GPP_S02 : [] ==> DMIC_SOC_CLK0_WLAN_PCM_OUT */
 324         PAD_CFG_NF(GPP_S02, NONE, DEEP, NF3),
 325         /* GPP_S03 : [] ==> DMIC_SOC_DATA0_WLAN_PCM_IN */
 326         PAD_CFG_NF(GPP_S03, NONE, DEEP, NF3),
 327         /* GPP_S04 : Not connected. */
 328         PAD_NC(GPP_S04, NONE),
 329         /* GPP_S05 : Not connected. */
 330         PAD_NC(GPP_S05, NONE),
 331         /* GPP_S06 : [] ==> DMIC_SOC_CLK1_DB_RC */
 332         PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
 333         /* GPP_S07 : [] ==> DMIC_SOC_DATA1_DB */
 334         PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
 335
 336         /* GPP_V00 : [] ==> BATLOW_L */
 337         PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
 338         /* GPP_V01 : [] ==> ACPRESENT */
 339         PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
 340         /* GPP_V02 : [] ==> EC_SOC_WAKE_ODL */
 341         PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
 342         /* GPP_V03 : [] ==> EC_SOC_PWR_BTN_ODL */
 343         PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
 344         /* GPP_V04 : [] ==> SLP_S3_L */
 345         PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
 346         /* GPP_V05 : [] ==> SLP_S4_L */
 347         PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
 348         /* GPP_V06 : [] ==> SOC_SLP_A_L */
 349         PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
 350         /* GPP_V08 : [] ==> SOC_SUSCLK */
 351         PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
 352         /* GPP_V09 : [] ==> SOC_SLP_WLAN_L */
 353         PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
 354         /* GPP_V10 : [] ==> SLP_S5_L */
 355         PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
 356         /* GPP_V11 : [] ==> SOC_GPP_V11 testpoint*/
 357         PAD_NC(GPP_V11, NONE),
 358         /* GPP_V12 : [] ==> SOC_SLP_LAN_L */
 359         PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
 360         /* GPP_V14 : [] ==> SOC_WAKE_L */
 361         PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
 362         /* GPP_V22 : NC net. */
 363         PAD_NC(GPP_V22, NONE),
 364         /* GPP_V23 : [] ==> UCAM_RST_L */
 365         PAD_CFG_GPO(GPP_V23, 0, DEEP),
 366 };
 367
 368 /* Early pad configuration in bootblock */
 369 static const struct pad_config early_gpio_table[] = {
 370         /* GPP_A20 : [] ==> SSD_PERST_L */
 371         PAD_CFG_GPO(GPP_A20, 0, DEEP),
 372
 373         /* GPP_B16 : [] ==> SOC_HDMI_HPD_L */
 374         PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
 375         /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */
 376         PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2),
 377         /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */
 378         PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2),
 379         /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */
 380         PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT),
 381
 382         /* GPP_E14 : [] ==> SOC_EDP_HPD_L */
 383         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 384         /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */
 385         PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
 386         /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */
 387         PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
 388
 389         /* GPP_H16 : [] ==> DDIB_HDMI_CTRLCLK*/
 390         PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
 391         /* GPP_H17 : [] ==> DDIB_HDMI_CTRLDATA */
 392         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 393         /* GPP_D03 : Not Connected */
 394         PAD_NC(GPP_D03, NONE),
 395
 396         /* GPP_E13 :  [] ==> MEM_CH_SEL */
 397         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 398
 399         /* GPP_H10 : [] ==> SOC_WP_OD */
 400         PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG),
 401
 402         /* GPP_C00 : [] ==> EN_TCHSCR_PWR */
 403         PAD_CFG_GPO(GPP_C00, 1, DEEP),
 404         /* GPP_C01 : [] ==> SOC_TCHSCR_RST_R_L */
 405         PAD_CFG_GPO(GPP_C01, 0, DEEP),
 406
 407         /* GPP_A19 : [] ==> EN_PP3300_SSD */
 408         PAD_CFG_GPO(GPP_A19, 1, DEEP),
 409 };
 410
 411 static const struct pad_config romstage_gpio_table[] = {
 412         /* GPP_B11 : [] ==> EN_FP_PWR */
 413         PAD_CFG_GPO(GPP_B11, 0, DEEP),
 414         /* GPP_C23 : [] ==> FP_RST_ODL */
 415         PAD_CFG_GPO(GPP_C23, 0, DEEP),
 416         /* GPP_C00 : [] ==> EN_TCHSCR_PWR */
 417         PAD_CFG_GPO(GPP_C00, 1, DEEP),
 418         /* GPP_C01 : [] ==> SOC_TCHSCR_RST_R_L */
 419         PAD_CFG_GPO(GPP_C01, 0, DEEP),
 420         /* GPP_D02 : Not Connected */
 421         PAD_NC(GPP_D02, NONE),
 422         /* GPP_A20 : [] ==> SSD_PERST_L */
 423         PAD_CFG_GPO(GPP_A20, 1, DEEP),
 424 };
 425
 426 const struct pad_config *variant_gpio_table(size_t *num)
 427 {
 428         *num = ARRAY_SIZE(gpio_table);
 429         return gpio_table;
 430 }
 431
 432 const struct pad_config *variant_early_gpio_table(size_t *num)
 433 {
 434         *num = ARRAY_SIZE(early_gpio_table);
 435         return early_gpio_table;
 436 }
 437
 438 /* Create the stub for romstage gpio, typically use for power sequence */
 439 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 440 {
 441         *num = ARRAY_SIZE(romstage_gpio_table);
 442         return romstage_gpio_table;
 443 }
 444
 445 static const struct cros_gpio cros_gpios[] = {
 446         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
 447         CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
 448 };
 449
 450 DECLARE_CROS_GPIOS(cros_gpios);