src/mainboard/google/rex/variants/screebo/variant.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/variants.h>
   4 #include <chip.h>
   5 #include <ec/google/chromeec/ec.h>
   6 #include <fw_config.h>
   7 #include <sar.h>
   8
   9 const char *get_wifi_sar_cbfs_filename(void)
  10 {
  11         return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID));
  12 }
  13
  14 void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config)
  15 {
  16         if (fw_config_probe(FW_CONFIG(AUDIO, ALC1019_ALC5682I_I2S)))
  17                 config->cnvi_bt_audio_offload = true;
  18
  19     /* SOC Aux orientation override:
  20         * This is a bitfield that corresponds to up to 4 TCSS ports.
  21         * Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
  22         * TcssAuxOri = 0101b
  23         * Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
  24         * Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
  25         * motherboard to USBC connector
  26     */
  27         if (fw_config_probe(FW_CONFIG(MB_CONFIG, MB_TYPEC))) {
  28                 config->typec_aux_bias_pads[1].pad_auxp_dc = GPP_C16;
  29                 config->typec_aux_bias_pads[1].pad_auxn_dc = GPP_C17;
  30                 config->tcss_aux_ori = 0x04;
  31         }
  32 }
  33
  34 const struct cpu_tdp_power_limits variant_perf_efficient_limits[] = {
  35         {
  36                 .mch_id = PCI_DID_INTEL_MTL_P_ID_2,
  37                 .cpu_tdp = 15,
  38                 .pl1_min_power = 10000,
  39                 .pl1_max_power = 15000,
  40                 .pl2_min_power = 40000,
  41                 .pl2_max_power = 40000,
  42                 .pl4_power = 84000
  43         },
  44         {
  45                 .mch_id = PCI_DID_INTEL_MTL_P_ID_5,
  46                 .cpu_tdp = 15,
  47                 .pl1_min_power = 10000,
  48                 .pl1_max_power = 15000,
  49                 .pl2_min_power = 40000,
  50                 .pl2_max_power = 40000,
  51                 .pl4_power = 84000
  52         },
  53 };
  54
  55 const struct cpu_tdp_power_limits variant_power_efficient_limits[] = {
  56         {
  57                 .mch_id = PCI_DID_INTEL_MTL_P_ID_2,
  58                 .cpu_tdp = 15,
  59                 .pl1_min_power = 10000,
  60                 .pl1_max_power = 15000,
  61                 .pl2_min_power = 40000,
  62                 .pl2_max_power = 40000,
  63                 .pl4_power = 47000
  64         },
  65         {
  66                 .mch_id = PCI_DID_INTEL_MTL_P_ID_5,
  67                 .cpu_tdp = 15,
  68                 .pl1_min_power = 10000,
  69                 .pl1_max_power = 15000,
  70                 .pl2_min_power = 40000,
  71                 .pl2_max_power = 40000,
  72                 .pl4_power = 47000
  73         },
  74 };
  75
  76 void variant_devtree_update(void)
  77 {
  78         const struct cpu_tdp_power_limits *limits = variant_perf_efficient_limits;
  79         size_t limits_size = ARRAY_SIZE(variant_perf_efficient_limits);
  80
  81         /*
  82          * If battery is not present or battery level is at or below critical threshold
  83          * to boot a platform with the performance efficient configuration, boot with
  84          * the power optimized configuration.
  85          */
  86         if (CONFIG(EC_GOOGLE_CHROMEEC)) {
  87                 if (!google_chromeec_is_battery_present_and_above_critical_threshold()) {
  88                         limits = variant_power_efficient_limits;
  89                         limits_size = ARRAY_SIZE(variant_power_efficient_limits);
  90                 }
  91         }
  92
  93         variant_update_cpu_power_limits(limits, limits_size);
  94 }