src/mainboard/google/slippy/smihandler.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <cpu/x86/smm.h>
   5 #include <southbridge/intel/lynxpoint/pch.h>
   6 #include <southbridge/intel/common/gpio.h>
   7 #include <southbridge/intel/lynxpoint/me.h>
   8 #include <northbridge/intel/haswell/haswell.h>
   9 #include <cpu/intel/haswell/haswell.h>
  10
  11 /* Include EC functions */
  12 #include <ec/google/chromeec/smm.h>
  13 #include "ec.h"
  14
  15 /* Codec enable: GPIO45 */
  16 #define GPIO_PP3300_CODEC_EN 45
  17 /* GPIO46 controls the WLAN_DISABLE_L signal. */
  18 #define GPIO_WLAN_DISABLE_L 46
  19 #define GPIO_LTE_DISABLE_L  59
  20
  21 /* gpi_sts is GPIO 47:32 */
  22 void mainboard_smi_gpi(u32 gpi_sts)
  23 {
  24         if (gpi_sts & (1 << (EC_SMI_GPI - 32)))
  25                 chromeec_smi_process_events();
  26 }
  27
  28 void mainboard_smi_sleep(u8 slp_typ)
  29 {
  30         /* Disable USB charging if required */
  31         chromeec_set_usb_charge_mode(slp_typ);
  32
  33         switch (slp_typ) {
  34         case ACPI_S3:
  35         case ACPI_S4:
  36         case ACPI_S5:
  37                 /* Prevent leak from standby rail to WLAN rail in S3/S4/S5. */
  38                 set_gpio(GPIO_WLAN_DISABLE_L, 0);
  39                 set_gpio(GPIO_PP3300_CODEC_EN, 0);
  40                 /* Disable LTE */
  41                 set_gpio(GPIO_LTE_DISABLE_L, 0);
  42                 break;
  43         }
  44
  45         chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
  46 }
  47
  48 int mainboard_smi_apmc(u8 apmc)
  49 {
  50         chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
  51         return 0;
  52 }