soc/intel/xeon_sp: Allow OS to control LTR and AER
[coreboot2.git] / src / mainboard / google / stout / Kconfig
blobb0f635210b0c88b49a0f6ab0659a3186e2575d4c
1 ## SPDX-License-Identifier: GPL-2.0-only
3 if BOARD_GOOGLE_STOUT
5 config BOARD_SPECIFIC_OPTIONS
6         def_bool y
7         select ACPI_GNVS_USB_CHARGECTL
8         select BOARD_ROMSIZE_KB_8192
9         select EC_QUANTA_IT8518
10         select GFX_GMA_PANEL_1_ON_LVDS
11         select HAVE_ACPI_RESUME
12         select HAVE_ACPI_TABLES
13         select HAVE_CMOS_DEFAULT
14         select HAVE_IFD_BIN
15         select HAVE_ME_BIN
16         select HAVE_OPTION_TABLE
17         select INTEL_INT15
18         select MAINBOARD_HAS_CHROMEOS
19         select MAINBOARD_HAS_LIBGFXINIT
20         select MEMORY_MAPPED_TPM
21         select MAINBOARD_HAS_TPM1
22         select NORTHBRIDGE_INTEL_SANDYBRIDGE
23         select SANDYBRIDGE_VBOOT_IN_ROMSTAGE
24         select SOUTHBRIDGE_INTEL_C216
25         select SYSTEM_TYPE_LAPTOP
27 config VBOOT
28         select VBOOT_VBNV_CMOS
30 config MAINBOARD_DIR
31         default "google/stout"
33 config MAINBOARD_PART_NUMBER
34         default "Stout"
36 config VGA_BIOS_ID
37         string
38         default "8086,0156"
40 config MAINBOARD_SMBIOS_MANUFACTURER
41         string
42         default "GOOGLE"
44 endif # BOARD_GOOGLE_STOUT