soc/intel/xeon_sp: Allow OS to control LTR and AER
[coreboot2.git] / src / mainboard / google / stout / dsdt.asl
blob89958c92565bb1d7a3ceb9ae84231db5442dcdb5
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <acpi/acpi.h>
4 #include <acpi/acpi.h>
5 DefinitionBlock(
6         "dsdt.aml",
7         "DSDT",
8         ACPI_DSDT_REV_2,
9         OEM_ID,
10         ACPI_TABLE_CREATOR,
11         0x20110725  // OEM revision
14         #include <acpi/dsdt_top.asl>
15         #include <southbridge/intel/common/acpi/platform.asl>
17         #include "acpi/platform.asl"
18         #include "acpi/mainboard.asl"
20         // Thermal handler
21         #include "acpi/thermal.asl"
23         // global NVS and variables
24         #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
26         #include <cpu/intel/common/acpi/cpu.asl>
28         Scope (\_SB) {
29                 Device (PCI0)
30                 {
31                         #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
32                         #include <southbridge/intel/bd82x6x/acpi/pch.asl>
34                         #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
35                 }
36         }
38         #include <southbridge/intel/common/acpi/sleepstates.asl>