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soc/intel/xeon_sp: Allow OS to control LTR and AER
[coreboot2.git] / src / mainboard / google / veyron / board_info.txt
blob5ee07fbd57a9edd8c8d922005454321afb9389a3
1 Vendor name: Google
2 Board name: Veyron Rockchip RK3288 boards
3 Category: misc
4 ROM protocol: SPI
5 ROM socketed: n
6 Flashrom support: y
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