mb/starlabs/starlite_adl: Configure CNVi Bluetooth I2S GPIOs
[coreboot2.git] / src / mainboard / google / veyron / boardid.c
blobf3d2abd88615a390d3141f03a7fb026e4635d09b
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <boardid.h>
4 #include <console/console.h>
5 #include <gpio.h>
7 uint32_t board_id(void)
9 static int id = -1;
10 gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
11 [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
13 if (id < 0) {
14 id = gpio_base2_value(pins, ARRAY_SIZE(pins));
15 printk(BIOS_SPEW, "Board ID: %d.\n", id);
18 return id;
21 uint32_t ram_code(void)
23 uint32_t code;
24 gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
25 [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
27 if (CONFIG(VEYRON_FORCE_BINARY_RAM_CODE))
28 code = gpio_base2_value(pins, ARRAY_SIZE(pins));
29 else
30 code = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins));
31 printk(BIOS_SPEW, "RAM Config: %u.\n", code);
33 return code;