src/mainboard/google/veyron/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <assert.h>
   5 #include <bootblock_common.h>
   6 #include <delay.h>
   7 #include <soc/clock.h>
   8 #include <soc/i2c.h>
   9 #include <soc/grf.h>
  10 #include <soc/pmu.h>
  11 #include <soc/rk808.h>
  12 #include <soc/spi.h>
  13 #include <vendorcode/google/chromeos/chromeos.h>
  14
  15 #include "board.h"
  16
  17 void bootblock_mainboard_early_init(void)
  18 {
  19         if (CONFIG(CONSOLE_SERIAL)) {
  20                 assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
  21                 write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
  22         }
  23 }
  24
  25 void bootblock_mainboard_init(void)
  26 {
  27         if (rkclk_was_watchdog_reset())
  28                 reboot_from_watchdog();
  29
  30         /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
  31         setbits32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
  32         setbits32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
  33         assert(CONFIG_PMIC_BUS == 0);   /* must correspond with IOMUX */
  34         i2c_init(CONFIG_PMIC_BUS, 400*KHz);
  35
  36         /* Slowly raise to max CPU voltage to prevent overshoot */
  37         rk808_configure_buck(1, 1200);
  38         udelay(175);/* Must wait for voltage to stabilize,2mV/us */
  39         rk808_configure_buck(1, 1400);
  40         udelay(100);/* Must wait for voltage to stabilize,2mV/us */
  41         rkclk_configure_cpu(APLL_1800_MHZ);
  42
  43         /* i2c1 for tpm */
  44         write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
  45         i2c_init(1, 400*KHz);
  46
  47         /* spi2 for firmware ROM */
  48         write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
  49         write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
  50         rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
  51
  52         /* spi0 for chrome ec */
  53         write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
  54         rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
  55
  56         setup_chromeos_gpios();
  57 }