src/mainboard/hardkernel/odroid-h4/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <gpio.h>
   4 #include <soc/gpio.h>
   5 #include <soc/ramstage.h>
   6
   7 /*
   8  * Pad configuration was derived from schematics, revision 0.1
   9  * - https://wiki.odroid.com/odroid-h4/hardware#odroid-h4_schematics
  10  */
  11 static const struct pad_config gpio_table[] = {
  12
  13         /* ------- GPIO Group GPP_A ------- */
  14         PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),    /* ESPI_IO0 */
  15         PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),    /* ESPI_IO1 */
  16         PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),    /* ESPI_IO2 */
  17         PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),    /* ESPI_IO3 */
  18         PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),    /* ESPI_CS# */
  19         PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),    /* ESPI_ALERT# */
  20         PAD_NC(GPP_A6, NONE),
  21         PAD_NC(GPP_A7, NONE),
  22         PAD_CFG_GPO(GPP_A8, 1, PLTRST),         /* LAN_DISABLE# */
  23         PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),    /* ESPI_CLK */
  24         PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),   /* ESPI_RESET# */
  25         PAD_NC(GPP_A11, NONE),
  26         PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),   /* M.2_SSD_PEDET_R */
  27         PAD_NC(GPP_A13, NONE),
  28         PAD_NC(GPP_A14, NONE),
  29         PAD_NC(GPP_A15, NONE),
  30         PAD_NC(GPP_A16, NONE),
  31         PAD_NC(GPP_A17, NONE),
  32         PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),   /* DDI1_HPD */
  33         PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),   /* TCP0_HPD */
  34         PAD_NC(GPP_A20, NONE),
  35         PAD_NC(GPP_A21, NONE),
  36         PAD_NC(GPP_A22, NONE),
  37         PAD_NC(GPP_A23, NONE),
  38
  39         /* ------- GPIO Group GPP_B ------- */
  40         PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),    /* CORE_VID0 */
  41         PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),    /* CORE_VID1 */
  42         PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1),  /* VRALERT# */
  43         PAD_NC(GPP_B3, NONE),
  44         PAD_NC(GPP_B4, NONE),
  45         PAD_NC(GPP_B5, NONE),
  46         PAD_NC(GPP_B6, NONE),
  47         PAD_NC(GPP_B7, NONE),
  48         PAD_CFG_GPI(GPP_B8, NONE, DEEP),        /* EMMC_DET#_L */
  49         PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),   /* PMCALERT# */
  50         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),   /* SLP_S0# */
  51         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),   /* PM_PLTRST_N */
  52         PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF4), /* PCH_SATA_LED# */
  53         PAD_NC(GPP_B15, NONE),
  54         PAD_NC(GPP_B16, NONE),
  55         PAD_NC(GPP_B17, NONE),
  56         PAD_NC(GPP_B18, NONE),
  57         PAD_NC(GPP_B23, NONE),
  58
  59         /* ------- GPIO Group GPP_C ------- */
  60         PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),    /* SMB_CLK */
  61         PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),    /* SMB_DATA */
  62         PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1),    /* SMB_ALERT# */
  63         PAD_NC(GPP_C3, NONE),
  64         PAD_NC(GPP_C4, NONE),
  65         PAD_NC(GPP_C5, NONE),
  66         PAD_NC(GPP_C6, NONE),
  67         PAD_NC(GPP_C7, NONE),
  68
  69         /* ------- GPIO Group GPP_D ------- */
  70         PAD_NC(GPP_D0, NONE),
  71         PAD_NC(GPP_D1, NONE),
  72         PAD_NC(GPP_D2, NONE),
  73         PAD_NC(GPP_D3, NONE),
  74         PAD_NC(GPP_D4, NONE),
  75         PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),    /* PCIE_CLKREQ0_N */
  76         PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),    /* PCIE_CLKREQ1_N */
  77         PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),    /* PCIE_CLKREQ2_N */
  78         PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),    /* CLKREQ3# but always asserted */
  79         PAD_NC(GPP_D9, NONE),
  80         PAD_NC(GPP_D10, NONE),
  81         PAD_NC(GPP_D11, NONE),
  82         PAD_NC(GPP_D11, NONE),
  83         PAD_NC(GPP_D13, NONE),
  84         PAD_NC(GPP_D14, NONE),
  85         PAD_NC(GPP_D15, NONE),
  86         PAD_NC(GPP_D16, NONE),
  87         PAD_NC(GPP_D17, NONE),
  88         PAD_NC(GPP_D18, NONE),
  89         PAD_NC(GPP_D19, NONE),
  90
  91         /* ------- GPIO Group GPP_E ------- */
  92         PAD_NC(GPP_E0, NONE),
  93         PAD_NC(GPP_E1, NONE),
  94         PAD_NC(GPP_E2, NONE),
  95         PAD_NC(GPP_E3, NONE),
  96         PAD_NC(GPP_E4, NONE),
  97         PAD_NC(GPP_E5, NONE),
  98         PAD_NC(GPP_E6, NONE),
  99         PAD_NC(GPP_E7, NONE),
 100         PAD_NC(GPP_E8, NONE),
 101         PAD_NC(GPP_E9, NONE),
 102         PAD_NC(GPP_E10, NONE),
 103         PAD_NC(GPP_E11, NONE),
 104         PAD_NC(GPP_E12, NONE),
 105         PAD_NC(GPP_E13, NONE),
 106         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),   /* DDI0_HPD */
 107         PAD_NC(GPP_E15, NONE),
 108         PAD_NC(GPP_E16, NONE),                  /* Unknown, goes to M.2 pin 67 (NC) */
 109         PAD_NC(GPP_E17, NONE),
 110         PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),   /* TCP0_DDCCLK */
 111         PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),   /* TCP0_DDCDATA */
 112         PAD_NC(GPP_E20, NONE),
 113         PAD_NC(GPP_E21, NONE),
 114         PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),   /* DDI0_DDCCLK */
 115         PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),   /* DDI0_DDCDATA */
 116
 117         /* ------- GPIO Group GPP_F ------- */
 118         PAD_NC(GPP_F0, NONE),
 119         PAD_NC(GPP_F1, NONE),
 120         PAD_NC(GPP_F2, NONE),
 121         PAD_NC(GPP_F3, NONE),
 122         PAD_NC(GPP_F4, NONE),
 123         PAD_NC(GPP_F5, NONE),
 124         PAD_NC(GPP_F6, NONE),
 125         PAD_NC(GPP_F7, NONE),
 126         PAD_NC(GPP_F10, NONE),
 127         PAD_NC(GPP_F11, NONE),
 128         PAD_NC(GPP_F12, NONE),
 129         PAD_NC(GPP_F13, NONE),
 130         PAD_NC(GPP_F14, NONE),
 131         PAD_NC(GPP_F15, NONE),
 132         PAD_NC(GPP_F16, NONE),
 133         PAD_NC(GPP_F17, NONE),
 134         PAD_NC(GPP_F18, NONE),
 135         PAD_NC(GPP_F22, NONE),
 136         PAD_NC(GPP_F23, NONE),
 137
 138         /* ------- GPIO Group GPP_H ------- */
 139         PAD_NC(GPP_H0, NONE),
 140         PAD_NC(GPP_H1, NONE),
 141         PAD_NC(GPP_H2, NONE),
 142         PAD_NC(GPP_H3, NONE),
 143         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),    /* I2C_0_SDA */
 144         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),    /* I2C_0_SCL */
 145         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),    /* I2C_1_SDA */
 146         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),    /* I2C_1_SCL */
 147         PAD_NC(GPP_H8, NONE),
 148         PAD_NC(GPP_H9, NONE),
 149         PAD_NC(GPP_H10, NONE),
 150         PAD_NC(GPP_H11, NONE),
 151         PAD_NC(GPP_H12, NONE),
 152         PAD_NC(GPP_H13, NONE),
 153         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),   /* DDI1_DDCCLK */
 154         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),   /* DDI1_DDCDATA */
 155         PAD_NC(GPP_H18, NONE),
 156         PAD_NC(GPP_H19, NONE),
 157         PAD_NC(GPP_H20, NONE),
 158         PAD_NC(GPP_H21, NONE),
 159         PAD_NC(GPP_H22, NONE),
 160         PAD_NC(GPP_H23, NONE),
 161
 162         /* ------- GPIO Group GPP_I ------- */
 163         PAD_NC(GPP_I5, NONE),
 164         PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),    /* EMMC_CMD */
 165         PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),    /* EMMC_DATA_0 */
 166         PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),    /* EMMC_DATA_1 */
 167         PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),   /* EMMC_DATA_2 */
 168         PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1),   /* EMMC_DATA_3 */
 169         PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1),   /* EMMC_DATA_4 */
 170         PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1),   /* EMMC_DATA_5 */
 171         PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1),   /* EMMC_DATA_6 */
 172         PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1),   /* EMMC_DATA_7 */
 173         PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1),   /* EMMC_RCLK */
 174         PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1),   /* EMMC_CLK */
 175         PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1),   /* EMMC_RESET# */
 176
 177         /* ------- GPIO Group GPP_R ------- */
 178         PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),    /* HDA_BCLK_R */
 179         PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),  /* HDA_SYNC_R */
 180         PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1),    /* HDA_SDO_R */
 181         PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),  /* HDA_SDI_R */
 182         PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),  /* HDA_RST_N */
 183         PAD_NC(GPP_R5, NONE),
 184         PAD_NC(GPP_R6, NONE),
 185         PAD_NC(GPP_R7, NONE),
 186
 187         /* ------- GPIO Group GPP_S ------- */
 188         PAD_NC(GPP_S0, NONE),
 189         PAD_NC(GPP_S1, NONE),
 190         PAD_NC(GPP_S2, NONE),
 191         PAD_NC(GPP_S3, NONE),
 192         PAD_NC(GPP_S4, NONE),
 193         PAD_NC(GPP_S5, NONE),
 194         PAD_NC(GPP_S6, NONE),
 195         PAD_NC(GPP_S7, NONE),
 196
 197         /* ------- GPIO Group GPP_GPD ------- */
 198         PAD_CFG_NF(GPD0, NONE, PWROK, NF1),     /* BATLOW# */
 199         PAD_CFG_NF(GPD1, NONE, PWROK, NF1),     /* ACPRESENT */
 200         PAD_NC(GPD2, NONE),
 201         PAD_CFG_NF(GPD3, NONE, PWROK, NF1),     /* PM_PWRBTN# */
 202         PAD_CFG_NF(GPD4, NONE, PWROK, NF1),     /* SLP_S3# */
 203         PAD_CFG_NF(GPD5, NONE, PWROK, NF1),     /* SLP_S4# */
 204         PAD_CFG_NF(GPD6, NONE, PWROK, NF1),     /* SLP_A# */
 205         PAD_NC(GPD7, NONE),
 206         PAD_CFG_NF(GPD8, NONE, PWROK, NF1),     /* SUSCLK */
 207         PAD_CFG_NF(GPD9, NONE, PWROK, NF1),     /* SLP_WLAN# */
 208         PAD_CFG_NF(GPD10, NONE, PWROK, NF1),    /* SLP_S5# */
 209         PAD_NC(GPD11, NONE),
 210 };
 211
 212 static void mainboard_init(void *chip_info)
 213 {
 214         gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 215 }
 216
 217 struct chip_operations mainboard_ops = {
 218         .init = mainboard_init,
 219 };