src/mainboard/intel/emeraldlake2/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <stdint.h>
   5 #include <arch/io.h>
   6 #include <superio/smsc/sio1007/sio1007.h>
   7 #include <northbridge/intel/sandybridge/raminit.h>
   8
   9 #define SIO_PORT 0x164e
  10
  11 void bootblock_mainboard_early_init(void)
  12 {
  13         const u16 port = SIO_PORT;
  14         const u16 runtime_port = 0x180;
  15
  16         sio1007_enable_uart_at(port);
  17
  18         /* Turn on configuration mode. */
  19         outb(0x55, port);
  20
  21         /* Set the GPIO direction, polarity, and type. */
  22         sio1007_setreg(port, 0x31, 1 << 0, 1 << 0);
  23         sio1007_setreg(port, 0x32, 0 << 0, 1 << 0);
  24         sio1007_setreg(port, 0x33, 0 << 0, 1 << 0);
  25
  26         /* Set the base address for the runtime register block. */
  27         sio1007_setreg(port, 0x30, runtime_port >> 4, 0xff);
  28         sio1007_setreg(port, 0x21, runtime_port >> 12, 0xff);
  29
  30         /* Turn on address decoding for it. */
  31         sio1007_setreg(port, 0x3a, 1 << 1, 1 << 1);
  32
  33         /* Set the value of GPIO 10 by changing GP1, bit 0. */
  34         u8 byte;
  35         byte = inb(runtime_port + 0xc);
  36         byte |= (1 << 0);
  37         outb(byte, runtime_port + 0xc);
  38
  39         /* Turn off address decoding for it. */
  40         sio1007_setreg(port, 0x3a, 0 << 1, 1 << 1);
  41
  42         /* Turn off configuration mode. */
  43         outb(0xaa, port);
  44 }
  45
  46 void mainboard_fill_pei_data(struct pei_data *pei_data)
  47 {
  48 }