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libpayload: configs: Add new config.featuretest to broaden CI
[coreboot2.git] / src / mainboard / intel / jasperlake_rvp / variants / jslrvp / devicetree.cb
blob1495366a88a820340c1bc3614c43f6f8415cdcf5
1 chip soc/intel/jasperlake
2
3 device cpu_cluster 0 on end
4
5 # GPE configuration
6 # Note that GPE events called out in ASL code rely on this
7 # route. i.e. If this route changes then the affected GPE
8 # offset bits also need to be changed.
9 register "pmc_gpe0_dw0" = "GPP_B"
10 register "pmc_gpe0_dw1" = "GPP_H"
11 register "pmc_gpe0_dw2" = "GPP_E"
12
13 # FSP configuration
14 register "SaGv" = "SaGv_Enabled"
15 register "SmbusEnable" = "1"
16 register "ScsEmmcHs400Enabled" = "1"
17 register "SdCardPowerEnableActiveHigh" = "1"
18
19 # Display related UPDs
20 # Select eDP for port A (1 = eDP, 2 = MIPI)
21 register "DdiPortAConfig" = "1"
22
23 # Enable HPD for DDI ports B/C
24 register "DdiPortBHpd" = "1"
25 register "DdiPortCHpd" = "1"
26
27 # Enable DDC for DDI ports B/C
28 register "DdiPortBDdc" = "1"
29 register "DdiPortCDdc" = "1"
30
31 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port1
32 register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # USB2 Type A port1
33 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port2
34 register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB2 Type A port2
35 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth
36 register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN
37 register "usb2_ports[6]" = "USB2_PORT_MID(OC2)" # USB2 Type A port3
38 register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" # USB2 Type A port4
39
40 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port1
41 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port2
42 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1
43 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # USB3 WWAN
44 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # UNUSED
45 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED
46
47 # Enable Pch iSCLK
48 register "pch_isclk" = "1"
49
50 # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
51 register "gen1_dec" = "0x00fc0801"
52 register "gen2_dec" = "0x000c0201"
53 # EC memory map range is 0x900-0x9ff
54 register "gen3_dec" = "0x00fc0901"
55
56 # Skip the CPU replacement check
57 register "SkipCpuReplacementCheck" = "1"
58
59 register "PchHdaDspEnable" = "1"
60 register "PchHdaAudioLinkHdaEnable" = "0"
61 register "PchHdaAudioLinkSspEnable[0]" = "1"
62 register "PchHdaAudioLinkSspEnable[1]" = "1"
63 register "PchHdaAudioLinkDmicEnable[0]" = "1"
64 register "PchHdaAudioLinkDmicEnable[1]" = "1"
65
66 # Enable ClkReqDetect 1 for WLAN
67 # Enable ClkReqDetect 4 for NVMe
68 register "PcieRpClkReqDetect[1]" = "1"
69 register "PcieRpClkReqDetect[4]" = "1"
70
71 register "PcieClkSrcUsage[0]" = "0x04"
72 register "PcieClkSrcUsage[1]" = "0x01"
73 register "PcieClkSrcUsage[2]" = "0xFF"
74 register "PcieClkSrcUsage[3]" = "0xFF"
75 register "PcieClkSrcUsage[4]" = "0xFF"
76 register "PcieClkSrcUsage[5]" = "0xFF"
77
78 register "PcieClkSrcClkReq[0]" = "0x00"
79 register "PcieClkSrcClkReq[1]" = "0x01"
80 register "PcieClkSrcClkReq[2]" = "0x02"
81 register "PcieClkSrcClkReq[3]" = "0x03"
82 register "PcieClkSrcClkReq[4]" = "0x04"
83 register "PcieClkSrcClkReq[5]" = "0x05"
84
85 register "SerialIoI2cMode" = "{
86 [PchSerialIoIndexI2C0] = PchSerialIoPci,
87 [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
88 [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
89 [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
90 [PchSerialIoIndexI2C4] = PchSerialIoPci,
91 [PchSerialIoIndexI2C5] = PchSerialIoPci,
92 }"
93
94 register "SerialIoGSpiMode" = "{
95 [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
96 [PchSerialIoIndexGSPI1] = PchSerialIoPci,
97 [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
98 }"
99
100 register "SerialIoGSpiCsMode" = "{
101 [PchSerialIoIndexGSPI0] = 1,
102 [PchSerialIoIndexGSPI1] = 1,
103 [PchSerialIoIndexGSPI2] = 1,
104 }"
105
106 register "SerialIoGSpiCsState" = "{
107 [PchSerialIoIndexGSPI0] = 0,
108 [PchSerialIoIndexGSPI1] = 0,
109 [PchSerialIoIndexGSPI2] = 0,
110 }"
111
112 register "SerialIoUartMode" = "{
113 [PchSerialIoIndexUART0] = PchSerialIoDisabled,
114 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
115 [PchSerialIoIndexUART2] = PchSerialIoSkipInit,
116 }"
117
118 # Enable DPTF
119 register "dptf_enable" = "1"
120
121 # Add PL1 and PL2 values
122 register "power_limits_config[JSL_N4500_6W_CORE]" = "{
123 .tdp_pl1_override = 6,
124 .tdp_pl2_override = 20,
125 }"
126
127 register "power_limits_config[JSL_N6000_6W_CORE]" = "{
128 .tdp_pl1_override = 6,
129 .tdp_pl2_override = 20,
130 }"
131
132 register "power_limits_config[JSL_N5100_6W_CORE]" = "{
133 .tdp_pl1_override = 6,
134 .tdp_pl2_override = 20,
135 }"
136
137 register "power_limits_config[JSL_N4505_10W_CORE]" = "{
138 .tdp_pl1_override = 10,
139 .tdp_pl2_override = 25,
140 }"
141
142 register "power_limits_config[JSL_N5105_10W_CORE]" = "{
143 .tdp_pl1_override = 10,
144 .tdp_pl2_override = 25,
145 }"
146
147 register "power_limits_config[JSL_N6005_10W_CORE]" = "{
148 .tdp_pl1_override = 10,
149 .tdp_pl2_override = 25,
150 }"
151
152 # Enable S0ix
153 register "s0ix_enable" = "true"
154
155 # GPIO for SD card detect
156 register "sdcard_cd_gpio" = "VGPIO_39"
157
158 register "common_soc_config" = "{
159 .gspi[1] = {
160 .speed_mhz = 1,
161 .early_init = 1,
162 },
163 .i2c[0] = {
164 .speed = I2C_SPEED_FAST,
165 .speed_config[0] = {
166 .speed = I2C_SPEED_FAST,
167 .scl_lcnt = 176,
168 .scl_hcnt = 95,
169 .sda_hold = 36,
170 }
171 },
172 .i2c[4] = {
173 .speed = I2C_SPEED_FAST,
174 },
175 .i2c[5] = {
176 .speed = I2C_SPEED_FAST,
177 },
178 }"
179
180 # Set the minimum assertion width
181 register "PchPmSlpS3MinAssert" = "3" # 50ms
182 register "PchPmSlpS4MinAssert" = "1" # 1s
183 register "PchPmSlpSusMinAssert" = "3" # 1s
184 register "PchPmSlpAMinAssert" = "3" # 98ms
185
186 # NOTE: Duration programmed in the below register should never be smaller than the
187 # stretch duration programmed in the following registers -
188 # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
189 # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
190 # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
191 # - PM_CFG.SLP_LAN_MIN_ASST_WDTH
192 register "PchPmPwrCycDur" = "1" # 1s
193
194 # Set xHCI LFPS period sampling off time, the default is 9ms.
195 register "xhci_lfps_sampling_offtime_ms" = "9"
196
197 device domain 0 on
198 device pci 00.0 on end # Host Bridge
199 device pci 02.0 on end # Integrated Graphics Device
200 device pci 04.0 on
201 chip drivers/intel/dptf
202 register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)"
203 register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 119, SHUTDOWN)"
204
205 register "controls.power_limits.pl1" = "{
206 .min_power = 3000,
207 .max_power = 6000,
208 .time_window_min = 1 * MSECS_PER_SEC,
209 .time_window_max = 1 * MSECS_PER_SEC,
210 .granularity = 200,}"
211 register "controls.power_limits.pl2" = "{
212 .min_power = 20000,
213 .max_power = 20000,
214 .time_window_min = 1 * MSECS_PER_SEC,
215 .time_window_max = 1 * MSECS_PER_SEC,
216 .granularity = 1000,}"
217 device generic 0 on end
218 end
219 end # SA Thermal device
220
221 device pci 05.0 on
222 chip drivers/intel/mipi_camera
223 register "acpi_uid" = "0x50000"
224 register "acpi_name" = ""IPU0""
225 register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
226
227 register "cio2_num_ports" = "2"
228 register "cio2_lanes_used" = "{2,2}"
229 register "cio2_lane_endpoint[0]" = ""^I2C4.CAM0""
230 register "cio2_lane_endpoint[1]" = ""^I2C5.CAM1""
231 register "cio2_prt[0]" = "0"
232 register "cio2_prt[1]" = "2"
233 device generic 0 on end
234 end
235 end
236 device pci 12.0 off end # Thermal Subsystem
237 device pci 12.5 off end # UFS SCS
238 device pci 12.6 off end # GSPI #2
239 device pci 14.0 on
240 chip drivers/usb/acpi
241 register "desc" = ""Root Hub""
242 register "type" = "UPC_TYPE_HUB"
243 device usb 0.0 on
244 chip drivers/usb/acpi
245 register "desc" = ""USB3/2 Type-A Left Lower""
246 register "type" = "UPC_TYPE_A"
247 device usb 2.0 on end
248 end
249 chip drivers/usb/acpi
250 register "desc" = ""WWAN""
251 register "type" = "UPC_TYPE_INTERNAL"
252 device usb 2.1 on end
253 end
254 chip drivers/usb/acpi
255 register "desc" = ""Bluetooth""
256 register "type" = "UPC_TYPE_INTERNAL"
257 device usb 2.2 on end
258 end
259 chip drivers/usb/acpi
260 register "desc" = ""USB C Connector 1""
261 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
262 device usb 2.3 on end
263 end
264 chip drivers/usb/acpi
265 register "desc" = ""USB C Connector 2""
266 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
267 device usb 2.4 on end
268 end
269 chip drivers/usb/acpi
270 register "desc" = ""USB C Connector 3""
271 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
272 device usb 2.5 on end
273 end
274 chip drivers/usb/acpi
275 register "desc" = ""USB C Connector 4""
276 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
277 device usb 2.6 on end
278 end
279 chip drivers/usb/acpi
280 register "desc" = ""USB3/2 Type-A Left Upper""
281 register "type" = "UPC_TYPE_A"
282 device usb 2.7 on end
283 end
284 chip drivers/usb/acpi
285 register "desc" = ""USB3/2 Type-A Left Lower""
286 register "type" = "UPC_TYPE_A"
287 device usb 3.0 on end
288 end
289 chip drivers/usb/acpi
290 register "desc" = ""USB3/2 Type-A Left Upper""
291 register "type" = "UPC_TYPE_A"
292 device usb 3.1 on end
293 end
294 chip drivers/usb/acpi
295 register "desc" = ""WLAN""
296 register "type" = "UPC_TYPE_INTERNAL"
297 device usb 3.2 on end
298 end
299 chip drivers/usb/acpi
300 register "desc" = ""USB3 Port Unused1""
301 register "type" = "UPC_TYPE_INTERNAL"
302 device usb 3.3 on end
303 end
304 chip drivers/usb/acpi
305 register "desc" = ""USB3 Port Unused2""
306 register "type" = "UPC_TYPE_INTERNAL"
307 device usb 3.4 on end
308 end
309 chip drivers/usb/acpi
310 register "desc" = ""USB3 Port Unused3""
311 register "type" = "UPC_TYPE_INTERNAL"
312 device usb 3.5 on end
313 end
314 end
315 end
316 end # USB xHCI
317 device pci 14.1 off end # USB xDCI (OTG)
318 device pci 14.2 off end # PMC SRAM
319 device pci 14.3 on
320 chip drivers/wifi/generic
321 register "wake" = "GPE0_PME_B0"
322 device generic 0 on end
323 end
324 end # CNVi wifi
325 device pci 14.5 on end # SDCard
326 device pci 15.0 on
327 chip drivers/i2c/max98373
328 register "vmon_slot_no" = "4"
329 register "imon_slot_no" = "5"
330 register "uid" = "0"
331 register "desc" = ""RIGHT SPEAKER AMP""
332 register "name" = ""MAXR""
333 device i2c 31 on end
334 end
335 chip drivers/i2c/max98373
336 register "vmon_slot_no" = "6"
337 register "imon_slot_no" = "7"
338 register "uid" = "1"
339 register "desc" = ""LEFT SPEAKER AMP""
340 register "name" = ""MAXL""
341 device i2c 32 on end
342 end
343 chip drivers/i2c/da7219
344 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H16_IRQ)"
345 register "btn_cfg" = "50"
346 register "mic_det_thr" = "500"
347 register "jack_ins_deb" = "20"
348 register "jack_det_rate" = ""32ms_64ms""
349 register "jack_rem_deb" = "1"
350 register "a_d_btn_thr" = "0xa"
351 register "d_b_btn_thr" = "0x16"
352 register "b_c_btn_thr" = "0x21"
353 register "c_mic_btn_thr" = "0x3e"
354 register "btn_avg" = "4"
355 register "adc_1bit_rpt" = "1"
356 register "micbias_lvl" = "2600"
357 register "mic_amp_in_sel" = ""diff""
358 device i2c 1a on end
359 end
360 end # I2C #0 Audio
361 device pci 15.1 off end # I2C #1
362 device pci 15.2 off end # I2C #2
363 device pci 15.3 off end # I2C #3
364 device pci 16.0 on end # Management Engine Interface 1
365 device pci 16.1 off end # Management Engine Interface 2
366 device pci 16.2 off end # Management Engine IDE-R
367 device pci 16.3 off end # Management Engine KT Redirection
368 device pci 16.4 off end # Management Engine Interface 3
369 device pci 16.5 off end # Management Engine Interface 4
370 device pci 17.0 off end # SATA
371 device pci 19.0 on # I2C #4 Cam 0
372 chip drivers/intel/mipi_camera
373 register "acpi_hid" = ""OVTI2740""
374 register "acpi_uid" = "0"
375 register "acpi_name" = ""CAM0""
376 register "chip_name" = ""Ov 2740 Camera""
377 register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
378 register "has_power_resource" = "1"
379
380 register "ssdb.lanes_used" = "2"
381 register "num_freq_entries" = "1"
382 register "link_freq[0]" = "360000000"
383 register "remote_name" = ""IPU0""
384
385 #Controls
386 register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_3
387 register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
388
389 register "gpio_panel.gpio[0].gpio_num" = "GPP_D5" #reset
390 register "gpio_panel.gpio[1].gpio_num" = "GPP_B14" #power
391
392 #_ON
393 register "on_seq.ops_cnt" = "4"
394 register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
395 register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
396 register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)"
397 register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
398
399 #_OFF
400 register "off_seq.ops_cnt" = "3"
401 register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
402 register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
403 register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
404
405 device i2c 10 on end
406 end
407 end
408 device pci 19.1 on # I2C #5 Cam 1 and VCM
409 chip drivers/intel/mipi_camera
410 register "acpi_hid" = ""OVTI5675""
411 register "acpi_uid" = "0"
412 register "acpi_name" = ""CAM1""
413 register "chip_name" = ""Ov 5675 Camera""
414 register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
415
416 register "ssdb.lanes_used" = "2"
417 register "ssdb.link_used" = "1"
418 register "ssdb.vcm_type" = "0x0C"
419 register "vcm_name" = ""VCM0""
420 register "num_freq_entries" = "1"
421 register "link_freq[0]" = "DEFAULT_LINK_FREQ"
422 register "remote_name" = ""IPU0""
423
424 register "has_power_resource" = "1"
425 #Controls
426 register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_3
427 register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
428
429 register "gpio_panel.gpio[0].gpio_num" = "GPP_D4" #power_enable
430 register "gpio_panel.gpio[1].gpio_num" = "GPP_C19" #reset
431
432 #_ON
433 register "on_seq.ops_cnt" = "4"
434 register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
435 register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
436 register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)"
437 register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
438
439 #_OFF
440 register "off_seq.ops_cnt" = "3"
441 register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
442 register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
443 register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
444
445 device i2c 36 on end
446 end
447 chip drivers/intel/mipi_camera
448 register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
449 register "acpi_uid" = "3"
450 register "acpi_name" = ""VCM0""
451 register "chip_name" = ""DW AF DAC""
452 register "device_type" = "INTEL_ACPI_CAMERA_VCM"
453
454 register "pr0" = ""\\_SB.PCI0.I2C5.CAM1.PRIC""
455 register "vcm_compat" = ""dongwoon,dw9714""
456
457 register "ssdb.lanes_used" = "2"
458 register "num_freq_entries" = "1"
459 register "link_freq[0]" = "DEFAULT_LINK_FREQ"
460 register "remote_name" = ""IPU0""
461 device i2c 0C on end
462 end
463 end
464
465 device pci 19.2 on end # UART #2
466 device pci 1a.0 on end # eMMC
467 device pci 1c.1 on end # PCI Express Port 2 - M.2 E-key WLAN
468 device pci 1c.4 on end # PCI Express Port 5 - NVMe
469 device pci 1e.0 on end # UART #0
470 device pci 1e.1 off end # UART #1
471 device pci 1e.2 off end # GSPI #0
472 device pci 1e.3 on
473 chip drivers/spi/acpi
474 register "hid" = "ACPI_DT_NAMESPACE_HID"
475 register "compat_string" = ""google,cr50""
476 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_H13_IRQ)"
477 device spi 0 on end
478 end
479 end # GSPI #1
480 device pci 1f.0 on end # eSPI Interface
481 device pci 1f.1 on end # P2SB
482 device pci 1f.2 hidden end # Power Management Controller
483 device pci 1f.3 on end # Intel HDA
484 device pci 1f.4 on end # SMBus
485 device pci 1f.5 on end # PCH SPI
486 device pci 1f.6 off end # GbE
487 end
488 end
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