src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <types.h>
   6 #include <vendorcode/google/chromeos/chromeos.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config gpio_table[] = {
  10         /* WWAN_WAKE_N */
  11         PAD_CFG_GPI_SCI(GPP_A10, NONE, DEEP, LEVEL, INVERT),
  12
  13         /* DDI1_HPD */
  14         PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
  15
  16         /* DDI0_HPD */
  17         PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
  18
  19         /* M.2_WWAN_DISABLE_N */
  20         PAD_CFG_GPO(GPP_A19, 1, PLTRST),
  21
  22         /* PMC_CORE_VID0 */
  23         PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
  24
  25         /* PMC_CORE_VID1 */
  26         PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
  27
  28         /* PMC_SLP_S0_N */
  29         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  30
  31         /* PMC_PLT_RST_N */
  32         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  33
  34         /* CAM1_RST_N */
  35         PAD_CFG_GPO(GPP_B14, 0, PLTRST),
  36
  37         /* M.2_WLAN_PERST_N */
  38         PAD_CFG_GPO(GPP_B17, 1, PLTRST),
  39
  40         /* GSPI1_CS0_N */
  41         PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
  42
  43         /* GSPI1_CLK */
  44         PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
  45
  46         /* GSPI1_MISO */
  47         PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
  48
  49         /* GSPI1_MOSI */
  50         PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
  51
  52         /* DDI2_HPD */
  53         PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),
  54
  55         /* WWAN_PERST_N */
  56         PAD_CFG_GPO(GPP_C0, 0, PLTRST),
  57
  58         /* M2_WWAN_SSD_SKT2_CFG2 */
  59         PAD_CFG_GPI(GPP_C3, NONE, PLTRST),
  60
  61         /* SLP_LAN_N */
  62         PAD_CFG_GPO(GPP_C7, 0, PLTRST),
  63
  64         /* I2C0_SDA */
  65         PAD_CFG_NF(GPP_C16, UP_2K, DEEP, NF1),
  66
  67         /* I2C0_SCL */
  68         PAD_CFG_NF(GPP_C17, UP_2K, DEEP, NF1),
  69
  70         /* CAM2_RST_N */
  71         PAD_CFG_GPO(GPP_C19, 0, PLTRST),
  72
  73         /* WIFI_RF_KILL_N */
  74         PAD_CFG_GPO(GPP_D0, 1, PLTRST),
  75
  76         /* BT_RF_KILL_N */
  77         PAD_CFG_GPO(GPP_D1, 1, PLTRST),
  78
  79         /* CAM2_PWREN */
  80         PAD_CFG_GPO(GPP_D4, 0, PLTRST),
  81
  82         /* CAM1_PWREN */
  83         PAD_CFG_GPO(GPP_D5, 0, PLTRST),
  84
  85         /*LAN_RST_N*/
  86         PAD_CFG_GPO(GPP_D6, 1, PLTRST),
  87
  88         /* I2C4B_SDA */
  89         PAD_CFG_NF(GPP_D12, NONE, DEEP, NF3),
  90
  91         /* I2C4B_SCL */
  92         PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3),
  93
  94         /* AVS_I2S_MCLK */
  95         PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
  96
  97         /* CNV_MFUART2_RXD */
  98         PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
  99
 100         /* CNV_MFUART2_TXD */
 101         PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
 102
 103         /* CNV_PA_BLANKING */
 104         PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
 105
 106         /* I2C5_SDA */
 107         PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1),
 108
 109         /* I2C5_SCL */
 110         PAD_CFG_NF(GPP_D23, NONE, PLTRST, NF1),
 111
 112         /* IMGCLKOUT_0 */
 113         PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2),
 114
 115         /* IMGCLKOUT_1 */
 116         PAD_CFG_NF(GPP_E2, NONE, PLTRST, NF1),
 117
 118         /* WWAN_FCP_OFF_N */
 119         PAD_CFG_GPO(GPP_E3, 1, PLTRST),
 120
 121         /* DDI0_DDC_SCL */
 122         PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
 123
 124         /* DDI0_DDC_SDA */
 125         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 126
 127         /* DDI1_DDC_SCL */
 128         PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
 129
 130         /* DDI1_DDC_SDA */
 131         PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1),
 132
 133         /* DDI2_DDC_SCL */
 134         PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 135
 136         /* DDI2_DDC_SDA */
 137         PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
 138
 139         /* CNV_BRI_DT */
 140         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
 141
 142         /* CNV_BRI_RSP */
 143         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
 144
 145         /* CNV_RGI_DT */
 146         PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
 147
 148         /* CNV_RGI_RSP */
 149         PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
 150
 151         /* CNV_RF_RESET_B */
 152         PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
 153
 154         /* EMMC_CMD */
 155         PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
 156
 157         /* EMMC_DATA0 */
 158         PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
 159
 160         /* EMMC_DATA1 */
 161         PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
 162
 163         /* EMMC_DATA2 */
 164         PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1),
 165
 166         /* EMMC_DATA3 */
 167         PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
 168
 169         /* EMMC_DATA4 */
 170         PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
 171
 172         /* EMMC_DATA5 */
 173         PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
 174
 175         /* EMMC_DATA6 */
 176         PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
 177
 178         /* EMMC_DATA7 */
 179         PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
 180
 181         /* EMMC_RCLK */
 182         PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
 183
 184         /* EMMC_CLK */
 185         PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
 186
 187         /* EMMC_RESET_N */
 188         PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
 189
 190         /* SD_SDIO_CMD */
 191         PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
 192
 193         /* SD_SDIO_D0 */
 194         PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
 195
 196         /* SD_SDIO_D1 */
 197         PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
 198
 199         /* SD_SDIO_D2 */
 200         PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
 201
 202         /* SD_SDIO_D3 */
 203         PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
 204
 205         /* SD_SDIO_CD_N */
 206         PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1),
 207
 208         /* SD_SDIO_CLK */
 209         PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
 210
 211         /* SD_SDIO_WP */
 212         PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1),
 213
 214         /* FPS_INT */
 215         PAD_CFG_GPI_APIC(GPP_H0, NONE, PLTRST, LEVEL, INVERT),
 216
 217         /* SD_SDIO_PWR_EN_N */
 218         PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
 219
 220         /* MODEM_CLKREQ0 */
 221         PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
 222
 223         /* WWAN EN GPIO */
 224         PAD_CFG_GPO(GPP_H7, 1, PLTRST),
 225
 226         /* CPU_C10_GATE_N */
 227         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
 228
 229         /* M.2_BT_I2S2_SCLK */
 230         PAD_CFG_GPI(GPP_H11, NONE, PLTRST),
 231
 232         /* CNV_RF_RESET_N */
 233         PAD_CFG_NF(GPP_H12, NONE, DEEP, NF2),
 234
 235         /* PCH_INT_ODL */
 236         PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT),
 237
 238         /* M.2_BT_I2S2_RXD */
 239         PAD_CFG_GPI(GPP_H14, NONE, PLTRST),
 240
 241         /* AVS_I2S1_SCLK */
 242         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
 243
 244         /* Audio Jack Detection */
 245         PAD_CFG_GPI_INT(GPP_H16, NONE, PLTRST, EDGE_BOTH),
 246
 247         /* M2_CNVI_EN_N */
 248         PAD_CFG_GPO(GPP_H19, 0, PLTRST),
 249
 250         /* AVS_I2S0_SCLK */
 251         PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
 252
 253         /* AVS_I2S0_SFRM */
 254         PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
 255
 256         /* AVS_I2S0_TXD */
 257         PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2),
 258
 259         /* AVS_I2S0_RXD */
 260         PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
 261
 262         /* AVS_I2S1_RXD */
 263         PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
 264
 265         /* AVS_I2S1_SFRM */
 266         PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1),
 267
 268         /* AVS_I2S1_TXD */
 269         PAD_CFG_NF(GPP_R7, NONE, DEEP, NF1),
 270
 271         /* WWAN RST_N */
 272         PAD_CFG_GPO(GPP_S0, 1, DEEP),
 273
 274         /* DMIC_CLK_1 */
 275         PAD_CFG_NF(GPP_S2, UP_20K, DEEP, NF2),
 276
 277         /* DMIC_DATA_1 */
 278         PAD_CFG_NF(GPP_S3, UP_20K, DEEP, NF2),
 279
 280         /* DMIC_CLK_0 */
 281         PAD_CFG_NF(GPP_S6, UP_20K, DEEP, NF2),
 282
 283         /* DMIC_DATA_0 */
 284         PAD_CFG_NF(GPP_S7, UP_20K, DEEP, NF2),
 285
 286         /* PMC_BATLOW_N */
 287         PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
 288
 289         /* PMC_ACPRESENT */
 290         PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
 291
 292         /* LAN_WAKE_N */
 293         PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
 294
 295         /* PMC_PWR_BTN_N */
 296         PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
 297
 298         /* PMC_SLP_S3_N */
 299         PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 300
 301         /* PMC_SLP_S4_N */
 302         PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 303
 304         /* PMC_SUSCLK */
 305         PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 306
 307         /* virtual GPIO for SD card detect */
 308         PAD_CFG_GPI_GPIO_DRIVER(VGPIO_39, NONE, DEEP),
 309 };
 310
 311 /* Early pad configuration in bootblock */
 312 static const struct pad_config early_gpio_table[] = {
 313 #if CONFIG(BOARD_INTEL_JASPERLAKE_RVP_EXT_EC)
 314         /* UART2 RX */
 315         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 316
 317         /* UART2 TX */
 318         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 319 #endif
 320
 321         /* GSPI1_CS# */
 322         PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
 323
 324         /* GSPI1_CLK */
 325         PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
 326
 327         /* GSPI1_MISO */
 328         PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
 329
 330         /* GSPI1_MOSI */
 331         PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
 332
 333         /* PCH_INT_ODL */
 334         PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT),
 335 };
 336
 337 const struct pad_config *variant_gpio_table(size_t *num)
 338 {
 339         *num = ARRAY_SIZE(gpio_table);
 340         return gpio_table;
 341 }
 342
 343 const struct pad_config *variant_early_gpio_table(size_t *num)
 344 {
 345         *num = ARRAY_SIZE(early_gpio_table);
 346         return early_gpio_table;
 347 }
 348
 349 static const struct cros_gpio cros_gpios[] = {
 350         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME),
 351 };
 352
 353 DECLARE_CROS_GPIOS(cros_gpios);