src/mainboard/inventec/transformers/include/sprsp_gpio.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef CFG_GPIO_H
   4 #define CFG_GPIO_H
   5
   6 #include <gpio.h>
   7
   8 /* Pad configuration was generated automatically using intelp2m utility */
   9 static const struct pad_config gpio_table[] = {
  10         /* ------- GPIO Community 0 ------- */
  11
  12         /* ------- GPIO Group GPPC_A ------- */
  13         _PAD_CFG_STRUCT(GPPC_A0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
  14         _PAD_CFG_STRUCT(GPPC_A1, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
  15         _PAD_CFG_STRUCT(GPPC_A2, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF), 0),
  16         _PAD_CFG_STRUCT(GPPC_A3, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | (1 << 1), 0),
  17         _PAD_CFG_STRUCT(GPPC_A4, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF), 0),
  18         _PAD_CFG_STRUCT(GPPC_A5, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF), 0),
  19         _PAD_CFG_STRUCT(GPPC_A6, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
  20         _PAD_CFG_STRUCT(GPPC_A7, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
  21         _PAD_CFG_STRUCT(GPPC_A8, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
  22         _PAD_CFG_STRUCT(GPPC_A9, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
  23         _PAD_CFG_STRUCT(GPPC_A10, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
  24         _PAD_CFG_STRUCT(GPPC_A11, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
  25         PAD_CFG_GPO(GPPC_A12, 1, RSMRST),
  26         PAD_NC(GPPC_A13, NONE),
  27         PAD_NC(GPPC_A14, NONE),
  28         PAD_CFG_GPO(GPPC_A15, 0, RSMRST),
  29         _PAD_CFG_STRUCT(GPPC_A16, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF), 0),
  30         PAD_NC(GPPC_A17, NONE),
  31         PAD_CFG_GPO(GPPC_A18, 1, RSMRST),
  32         /* GPPC_A19 - RESERVED */
  33
  34         /* ------- GPIO Group GPPC_B ------- */
  35         _PAD_CFG_STRUCT(GPPC_B0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
  36         _PAD_CFG_STRUCT(GPPC_B1, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
  37         _PAD_CFG_STRUCT(GPPC_B2, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
  38         _PAD_CFG_STRUCT(GPPC_B3, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
  39         _PAD_CFG_STRUCT(GPPC_B4, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
  40         PAD_NC(GPPC_B5, NONE),
  41         _PAD_CFG_STRUCT(GPPC_B6, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
  42         PAD_CFG_GPI_TRIG_OWN(GPPC_B7, NONE, RSMRST, OFF, ACPI),
  43         PAD_CFG_GPI_TRIG_OWN(GPPC_B8, NONE, RSMRST, OFF, ACPI),
  44         _PAD_CFG_STRUCT(GPPC_B9, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
  45         PAD_CFG_GPI_TRIG_OWN(GPPC_B10, NONE, RSMRST, OFF, ACPI),
  46         /* GPPC_B11 - n/a */
  47         PAD_NC(GPPC_B12, NONE),
  48         PAD_CFG_GPI_TRIG_OWN(GPPC_B13, NONE, RSMRST, OFF, ACPI),
  49         PAD_NC(GPPC_B14, NONE),
  50         PAD_NC(GPPC_B15, NONE),
  51         PAD_NC(GPPC_B16, NONE),
  52         PAD_NC(GPPC_B17, NONE),
  53         PAD_NC(GPPC_B18, NONE),
  54         PAD_NC(GPPC_B19, NONE),
  55         PAD_NC(GPPC_B20, NONE),
  56         PAD_NC(GPPC_B21, NONE),
  57         PAD_NC(GPPC_B22, NONE),
  58         _PAD_CFG_STRUCT(GPPC_B23, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
  59
  60         /* ------- GPIO Group GPPC_S ------- */
  61         PAD_NC(GPPC_S0, NONE),
  62         _PAD_CFG_STRUCT(GPPC_S1, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
  63         PAD_NC(GPPC_S2, NONE),
  64         PAD_CFG_GPO(GPPC_S3, 1, RSMRST),
  65         PAD_CFG_GPI_TRIG_OWN(GPPC_S4, NONE, RSMRST, OFF, ACPI),
  66         _PAD_CFG_STRUCT(GPPC_S5, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
  67         PAD_NC(GPPC_S6, NONE),
  68         _PAD_CFG_STRUCT(GPPC_S7, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
  69         _PAD_CFG_STRUCT(GPPC_S8, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
  70         _PAD_CFG_STRUCT(GPPC_S9, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
  71         _PAD_CFG_STRUCT(GPPC_S10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
  72         PAD_CFG_GPI_TRIG_OWN(GPPC_S11, NONE, RSMRST, OFF, ACPI),
  73
  74         /* ------- GPIO Community 1 ------- */
  75
  76         /* ------- GPIO Group GPPC_C ------- */
  77         /* GPPC_C0 - RESERVED */
  78         /* GPPC_C1 - RESERVED */
  79         _PAD_CFG_STRUCT(GPPC_C2, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),
  80         /* GPPC_C3 - RESERVED */
  81         /* GPPC_C4 - RESERVED */
  82         PAD_CFG_GPO(GPPC_C5, 0, DEEP),
  83         /* GPPC_C6 - RESERVED */
  84         /* GPPC_C7 - RESERVED */
  85         /* GPPC_C8 - RESERVED */
  86         /* GPPC_C9 - RESERVED */
  87         /* GPPC_C10 - RESERVED */
  88         /* GPPC_C11 - RESERVED */
  89         /* GPPC_C12 - RESERVED */
  90         /* GPPC_C13 - RESERVED */
  91         /* GPPC_C14 - RESERVED */
  92         /* GPPC_C15 - RESERVED */
  93         /* GPPC_C16 - RESERVED */
  94         PAD_CFG_GPO(GPPC_C17, 1, DEEP),
  95         PAD_CFG_GPO(GPPC_C18, 0, RSMRST),
  96         _PAD_CFG_STRUCT(GPPC_C19, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),
  97         _PAD_CFG_STRUCT(GPPC_C20, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | (1 << 1), 0),
  98         PAD_CFG_GPO(GPPC_C21, 0, DEEP),
  99
 100         /* ------- GPIO Group GPP_D ------- */
 101         _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),
 102         _PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | (1 << 1), 0),
 103         PAD_CFG_GPO(GPP_D2, 0, DEEP),
 104         PAD_NC(GPP_D3, UP_20K),
 105         PAD_NC(GPP_D4, UP_20K),
 106         PAD_NC(GPP_D5, UP_20K),
 107         PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, RSMRST, OFF, ACPI),
 108         PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, RSMRST, OFF, ACPI),
 109         _PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
 110         PAD_NC(GPP_D9, UP_20K),
 111         PAD_NC(GPP_D10, NONE),
 112         _PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
 113         _PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
 114         /* GPP_D13 - RESERVED */
 115         _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
 116         PAD_NC(GPP_D15, NONE),
 117         _PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
 118         _PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
 119         _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
 120         _PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
 121         _PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)),
 122         _PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
 123         _PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0),
 124         PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, RSMRST, OFF, ACPI),
 125
 126         /* ------- GPIO Community 3 ------- */
 127
 128         /* ------- GPIO Group GPP_E ------- */
 129         PAD_CFG_GPO(GPP_E0, 0, RSMRST),
 130         PAD_CFG_GPO(GPP_E1, 1, RSMRST),
 131         PAD_CFG_GPO(GPP_E2, 1, RSMRST),
 132         PAD_CFG_GPO(GPP_E3, 1, RSMRST),
 133         _PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
 134         _PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
 135         _PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
 136         _PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
 137         _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
 138         _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
 139         _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
 140         _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
 141         _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
 142         _PAD_CFG_STRUCT(GPP_E13, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
 143         PAD_CFG_GPO(GPP_E14, 0, RSMRST),
 144         PAD_NC(GPP_E15, NONE),
 145         PAD_NC(GPP_E16, NONE),
 146         _PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
 147         _PAD_CFG_STRUCT(GPP_E18, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
 148         _PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
 149         /* ------- GPIO Group JTAG ------- */
 150
 151         /* ------- GPIO Community 4 ------- */
 152
 153         /* ------- GPIO Group GPPC_H ------- */
 154         _PAD_CFG_STRUCT(GPPC_H0, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
 155         /* GPPC_H1 - RESERVED */
 156         PAD_NC(GPPC_H2, UP_20K),
 157         PAD_NC(GPPC_H3, UP_20K),
 158         PAD_NC(GPPC_H4, UP_20K),
 159         PAD_NC(GPPC_H5, UP_20K),
 160         _PAD_CFG_STRUCT(GPPC_H6, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
 161         _PAD_CFG_STRUCT(GPPC_H7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
 162         PAD_NC(GPPC_H8, UP_20K),
 163         PAD_NC(GPPC_H9, NONE),
 164         PAD_NC(GPPC_H10, NONE),
 165         PAD_NC(GPPC_H11, NONE),
 166         PAD_NC(GPPC_H12, UP_20K),
 167         PAD_NC(GPPC_H13, UP_20K),
 168         PAD_NC(GPPC_H14, UP_20K),
 169         _PAD_CFG_STRUCT(GPPC_H15, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
 170         _PAD_CFG_STRUCT(GPPC_H16, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
 171         _PAD_CFG_STRUCT(GPPC_H17, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
 172         PAD_NC(GPPC_H18, NONE),
 173         _PAD_CFG_STRUCT(GPPC_H19, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
 174
 175         /* ------- GPIO Group GPP_J ------- */
 176         _PAD_CFG_STRUCT(GPP_J0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
 177         _PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_1K)),
 178         _PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
 179         _PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
 180         _PAD_CFG_STRUCT(GPP_J4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
 181         _PAD_CFG_STRUCT(GPP_J5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
 182         _PAD_CFG_STRUCT(GPP_J6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_1K)),
 183         _PAD_CFG_STRUCT(GPP_J7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_1K)),
 184         _PAD_CFG_STRUCT(GPP_J8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
 185         PAD_NC(GPP_J9, DN_20K),
 186         PAD_NC(GPP_J10, DN_20K),
 187         PAD_NC(GPP_J11, DN_20K),
 188         PAD_NC(GPP_J12, UP_1K),
 189         PAD_NC(GPP_J13, UP_1K),
 190         PAD_NC(GPP_J14, UP_1K),
 191         PAD_NC(GPP_J15, UP_1K),
 192
 193         /* ------- GPIO Community 5 ------- */
 194
 195         /* ------- GPIO Group GPP_I ------- */
 196         PAD_NC(GPP_I0, UP_20K),
 197         PAD_NC(GPP_I1, UP_20K),
 198         PAD_NC(GPP_I2, UP_20K),
 199         PAD_NC(GPP_I3, UP_20K),
 200         PAD_NC(GPP_I4, UP_20K),
 201         PAD_NC(GPP_I5, UP_20K),
 202         PAD_NC(GPP_I6, UP_20K),
 203         PAD_NC(GPP_I7, UP_20K),
 204         PAD_NC(GPP_I8, UP_20K),
 205         PAD_CFG_TERM_GPO(GPP_I9, 0, UP_20K, DEEP),
 206         PAD_NC(GPP_I10, UP_20K),
 207         PAD_CFG_TERM_GPO(GPP_I11, 0, UP_20K, DEEP),
 208         _PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
 209         _PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
 210         _PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
 211         _PAD_CFG_STRUCT(GPP_I15, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
 212         _PAD_CFG_STRUCT(GPP_I16, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
 213         _PAD_CFG_STRUCT(GPP_I17, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
 214         PAD_CFG_TERM_GPO(GPP_I18, 0, UP_20K, DEEP),
 215         PAD_CFG_TERM_GPO(GPP_I19, 0, UP_20K, DEEP),
 216         PAD_CFG_TERM_GPO(GPP_I20, 0, UP_20K, DEEP),
 217         PAD_CFG_TERM_GPO(GPP_I21, 0, UP_20K, DEEP),
 218         _PAD_CFG_STRUCT(GPP_I22, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
 219         PAD_CFG_GPI_TRIG_OWN(GPP_I23, NONE, RSMRST, OFF, ACPI),
 220
 221         /* ------- GPIO Group GPP_L ------- */
 222         _PAD_CFG_STRUCT(GPP_L0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
 223         /* GPP_L1 - RESERVED */
 224         _PAD_CFG_STRUCT(GPP_L2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
 225         PAD_NC(GPP_L3, NONE),
 226         PAD_NC(GPP_L4, NONE),
 227         _PAD_CFG_STRUCT(GPP_L5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
 228         PAD_CFG_GPI_TRIG_OWN(GPP_L6, NONE, PLTRST, OFF, DRIVER),
 229         PAD_NC(GPP_L7, NONE),
 230         PAD_NC(GPP_L8, NONE),
 231
 232         /* ------- GPIO Group GPP_M ------- */
 233         PAD_CFG_GPI_TRIG_OWN(GPP_M0, NONE, PLTRST, OFF, ACPI),
 234         PAD_CFG_GPI_TRIG_OWN(GPP_M1, NONE, PLTRST, OFF, ACPI),
 235         PAD_CFG_GPI_TRIG_OWN(GPP_M2, NONE, PLTRST, OFF, ACPI),
 236         PAD_CFG_GPI_TRIG_OWN(GPP_M3, NONE, PLTRST, OFF, ACPI),
 237         PAD_CFG_GPI_TRIG_OWN(GPP_M4, DN_20K, PLTRST, OFF, ACPI),
 238         PAD_CFG_GPI_TRIG_OWN(GPP_M5, NONE, PLTRST, OFF, ACPI),
 239         PAD_CFG_GPI_TRIG_OWN(GPP_M6, NONE, PLTRST, OFF, ACPI),
 240         PAD_CFG_GPI_TRIG_OWN(GPP_M7, NONE, PLTRST, OFF, ACPI),
 241         PAD_CFG_GPI_TRIG_OWN(GPP_M8, NONE, PLTRST, OFF, ACPI),
 242         PAD_NC(GPP_M9, DN_20K),
 243         PAD_NC(GPP_M10, DN_20K),
 244         PAD_CFG_GPI_TRIG_OWN(GPP_M11, NONE, RSMRST, OFF, ACPI),
 245         PAD_CFG_TERM_GPO(GPP_M12, 0, DN_20K, DEEP),
 246         PAD_NC(GPP_M13, DN_20K),
 247         PAD_NC(GPP_M14, DN_20K),
 248         PAD_NC(GPP_M15, UP_20K),
 249         PAD_NC(GPP_M16, UP_20K),
 250         PAD_NC(GPP_M17, UP_20K),
 251
 252         /* ------- GPIO Group GPP_N ------- */
 253         PAD_NC(GPP_N0, NONE),
 254         PAD_NC(GPP_N1, DN_20K),
 255         PAD_NC(GPP_N2, NONE),
 256         PAD_NC(GPP_N3, NONE),
 257         PAD_NC(GPP_N4, NONE),
 258 };
 259
 260 #endif /* CFG_GPIO_H */