src/mainboard/lattepanda/mu/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/variants.h>
   4 #include <soc/romstage.h>
   5
   6 static const struct mb_cfg mu_lp5_mem_config = {
   7         .type = MEM_TYPE_LP5X,
   8
   9         /* DQ byte map */
  10         .lpx_dq_map = {
  11                 .ddr0 = {
  12                         .dq0 = { 12, 10,  9, 11, 15, 14,  8, 13 },
  13                         .dq1 = {  0,  3,  1,  2,  7,  4,  6,  5 },
  14                 },
  15                 .ddr1 = {
  16                         .dq0 = {  0,  2,  1,  3,  4,  7,  5,  6 },
  17                         .dq1 = { 13, 11,  9, 10,  8, 15, 12, 14 },
  18                 },
  19                 .ddr2 = {
  20                         .dq0 = {  0,  1,  2,  3,  7,  4,  5,  6 },
  21                         .dq1 = {  9, 10,  8, 11, 14, 15, 12, 13 },
  22                 },
  23                 .ddr3 = {
  24                         .dq0 = {  3,  0,  1,  2,  5,  6,  4,  7 },
  25                         .dq1 = { 14, 10,  8, 11, 12, 15,  9, 13 },
  26                 },
  27                 .ddr4 = {
  28                         .dq0 = {  3,  0,  2,  1,  6,  7,  5,  4 },
  29                         .dq1 = { 12, 14, 15, 13,  9, 11,  8, 10 },
  30                 },
  31                 .ddr5 = {
  32                         .dq0 = {  0,  1,  2,  3,  6,  4,  5,  7 },
  33                         .dq1 = { 15, 14, 12, 13,  9, 11,  8, 10 },
  34                 },
  35                 .ddr6 = {
  36                         .dq0 = {  3,  0,  1,  2,  5,  4,  6,  7 },
  37                         .dq1 = { 12, 13, 15, 14,  9, 11, 10,  8 },
  38                 },
  39                 .ddr7 = {
  40                         .dq0 = {  3,  0,  2,  1,  5,  4,  6,  7 },
  41                         .dq1 = { 10,  8, 15, 14,  9, 12, 13, 11 },
  42                 },
  43         },
  44
  45         /* DQS CPU<>DRAM map */
  46         .lpx_dqs_map = {
  47                 .ddr0 = { .dqs0 = 1, .dqs1 = 0 },
  48                 .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
  49                 .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
  50                 .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
  51                 .ddr4 = { .dqs0 = 0, .dqs1 = 1 },
  52                 .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
  53                 .ddr6 = { .dqs0 = 0, .dqs1 = 1 },
  54                 .ddr7 = { .dqs0 = 0, .dqs1 = 1 }
  55         },
  56
  57         .ect = true, /* Early Command Training */
  58
  59         .UserBd = BOARD_TYPE_ULT_ULX,
  60
  61         .LpDdrDqDqsReTraining = 1,
  62
  63         .lp5x_config = {
  64                 .ccc_config = 0x00,
  65         },
  66 };
  67
  68 const struct mb_cfg *variant_memory_params(void)
  69 {
  70         return &mu_lp5_mem_config;
  71 }