src/mainboard/pcengines/apu2/BiosCallOuts.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <AGESA.h>
   4 #include <console/console.h>
   5 #include <spd_bin.h>
   6 #include <northbridge/amd/agesa/BiosCallOuts.h>
   7 #include <northbridge/amd/agesa/state_machine.h>
   8 #include <FchPlatform.h>
   9
  10 #include "gpio_ftns.h"
  11 #include "imc.h"
  12 #include "hudson.h"
  13
  14 static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
  15
  16 const BIOS_CALLOUT_STRUCT BiosCallouts[] =
  17 {
  18         {AGESA_READ_SPD,                 board_ReadSpd_from_cbfs },
  19         {AGESA_DO_RESET,                 agesa_Reset },
  20         {AGESA_READ_SPD_RECOVERY,        agesa_NoopUnsupported },
  21         {AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
  22         {AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
  23         {AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
  24         {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }
  25 };
  26 const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
  27
  28 //{AGESA_GNB_GFX_GET_VBIOS_IMAGE,  agesa_NoopUnsupported }
  29
  30 /*
  31  * Hardware Monitor Fan Control
  32  * Hardware limitation:
  33  *  HWM will fail to read the input temperature via I2C if other
  34  *  software switches the I2C address.  AMD recommends using IMC
  35  *  to control fans, instead of HWM.
  36  */
  37 static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
  38 {
  39         FchParams->Imc.ImcEnable = FALSE;
  40         FchParams->Hwm.HwMonitorEnable = FALSE;
  41         FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;                /* 1 enable, 0 disable TSI Auto Polling */
  42 }
  43
  44 void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams)
  45 {
  46         printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
  47         //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
  48         FchParams->LegacyFree = 0; /* don't clear LPC IO decodes for serial console */
  49         FchParams->FchReset.SataEnable = hudson_sata_enable();
  50         FchParams->FchReset.IdeEnable = hudson_ide_enable();
  51         FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
  52         FchParams->FchReset.Xhci1Enable = FALSE;
  53         printk(BIOS_DEBUG, "Done\n");
  54 }
  55
  56 void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams)
  57 {
  58         printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
  59
  60         FchParams->Azalia.AzaliaEnable = AzDisable;
  61
  62         /* Fan Control */
  63         oem_fan_control(FchParams);
  64
  65         /* XHCI configuration */
  66         FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
  67         FchParams->Usb.Xhci1Enable = FALSE;
  68
  69         /* EHCI configuration */
  70         FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE);
  71
  72         if (CONFIG(BOARD_PCENGINES_APU2)) {
  73                 // Disable EHCI 0 (port 0 to 3)
  74                 FchParams->Usb.Ehci1Enable = FALSE;
  75         } else {
  76                 // Enable EHCI 0 (port 0 to 3)
  77                 FchParams->Usb.Ehci1Enable = TRUE;
  78         }
  79
  80         // Enable EHCI 1 (port 4 to 7)
  81         // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
  82         FchParams->Usb.Ehci2Enable = TRUE;
  83
  84         /* sata configuration */
  85         // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
  86         FchParams->Sata.SataDevSlpPort0 = 0;
  87         FchParams->Sata.SataDevSlpPort1 = 0;
  88
  89         FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
  90         switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
  91         case SataRaid:
  92         case SataAhci:
  93         case SataAhci7804:
  94         case SataLegacyIde:
  95                 FchParams->Sata.SataIdeMode = FALSE;
  96                 break;
  97         case SataIde2Ahci:
  98         case SataIde2Ahci7804:
  99         default: /* SataNativeIde */
 100                 FchParams->Sata.SataIdeMode = TRUE;
 101                 break;
 102         }
 103         printk(BIOS_DEBUG, "Done\n");
 104 }
 105
 106 static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 107 {
 108         AGESA_READ_SPD_PARAMS   *info = ConfigPtr;
 109
 110         if (!ENV_RAMINIT)
 111                 return AGESA_UNSUPPORTED;
 112
 113         u8 index = get_spd_offset();
 114
 115         if (info->MemChannelId > 0)
 116                 return AGESA_UNSUPPORTED;
 117         if (info->SocketId != 0)
 118                 return AGESA_UNSUPPORTED;
 119         if (info->DimmId != 0)
 120                 return AGESA_UNSUPPORTED;
 121
 122         /* Read index 0, first SPD_SIZE bytes of spd.bin file. */
 123         if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0)
 124                 die("No SPD data\n");
 125
 126         return AGESA_SUCCESS;
 127 }