src/mainboard/samsung/stumpy/chromeos.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootmode.h>
   4 #include <boot/coreboot_tables.h>
   5 #include <device/pci_ops.h>
   6 #include <device/device.h>
   7 #include <southbridge/intel/bd82x6x/pch.h>
   8 #include <southbridge/intel/common/gpio.h>
   9 #include <types.h>
  10 #include <vendorcode/google/chromeos/chromeos.h>
  11 #include "onboard.h"
  12
  13 void fill_lb_gpios(struct lb_gpios *gpios)
  14 {
  15         struct lb_gpio chromeos_gpios[] = {
  16                 /* Recovery: GPIO42 = CHP3_REC_MODE# */
  17                 {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(),
  18                  "presence"},
  19
  20                 /* Hard code the lid switch GPIO to open. */
  21                 {100, ACTIVE_HIGH, 1, "lid"},
  22
  23                 /* Power Button */
  24                 {101, ACTIVE_LOW, get_power_switch(), "power"},
  25
  26                 /* Did we load the VGA Option ROM? */
  27                 /* -1 indicates that this is a pseudo GPIO */
  28                 {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
  29         };
  30         lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
  31 }
  32
  33 int get_write_protect_state(void)
  34 {
  35         return get_gpio(GPIO_SPI_WP);
  36 }
  37
  38 int get_recovery_mode_switch(void)
  39 {
  40         return !get_gpio(GPIO_REC_MODE);
  41 }
  42
  43 int get_power_switch(void)
  44 {
  45         const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
  46         u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1);
  47         return (gen_pmcon_1 >> 9) & 1;
  48 }
  49
  50 static const struct cros_gpio cros_gpios[] = {
  51         CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
  52         CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
  53 };
  54
  55 DECLARE_CROS_GPIOS(cros_gpios);