| blob | e77036b4d780b3a0513299793366639f4e1ec104 |
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /dts-v1/;
5 / {
6 #address-cells = <2>;
7 #size-cells = <2>;
8 compatible = "sifive,fu540-c000", "sifive,fu540";
10 aliases {
11 serial0 = &uart0;
12 serial1 = &uart1;
13 };
15 chosen {
16 };
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21 timebase-frequency = <1000000>;
22 cpu0: cpu@0 {
23 compatible = "sifive,e51", "sifive,rocket0", "riscv";
24 device_type = "cpu";
25 i-cache-block-size = <64>;
26 i-cache-sets = <128>;
27 i-cache-size = <16384>;
28 reg = <0>;
29 riscv,isa = "rv64imac";
30 status = "disabled";
31 cpu0_intc: interrupt-controller {
32 #interrupt-cells = <1>;
33 compatible = "riscv,cpu-intc";
34 interrupt-controller;
35 };
36 };
37 cpu1: cpu@1 {
38 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
39 d-cache-block-size = <64>;
40 d-cache-sets = <64>;
41 d-cache-size = <32768>;
42 d-tlb-sets = <1>;
43 d-tlb-size = <32>;
44 device_type = "cpu";
45 i-cache-block-size = <64>;
46 i-cache-sets = <64>;
47 i-cache-size = <32768>;
48 i-tlb-sets = <1>;
49 i-tlb-size = <32>;
50 mmu-type = "riscv,sv39";
51 reg = <1>;
52 riscv,isa = "rv64imafdc";
53 tlb-split;
54 cpu1_intc: interrupt-controller {
55 #interrupt-cells = <1>;
56 compatible = "riscv,cpu-intc";
57 interrupt-controller;
58 };
59 };
60 cpu2: cpu@2 {
61 clock-frequency = <0>;
62 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
63 d-cache-block-size = <64>;
64 d-cache-sets = <64>;
65 d-cache-size = <32768>;
66 d-tlb-sets = <1>;
67 d-tlb-size = <32>;
68 device_type = "cpu";
69 i-cache-block-size = <64>;
70 i-cache-sets = <64>;
71 i-cache-size = <32768>;
72 i-tlb-sets = <1>;
73 i-tlb-size = <32>;
74 mmu-type = "riscv,sv39";
75 reg = <2>;
76 riscv,isa = "rv64imafdc";
77 tlb-split;
78 cpu2_intc: interrupt-controller {
79 #interrupt-cells = <1>;
80 compatible = "riscv,cpu-intc";
81 interrupt-controller;
82 };
83 };
84 cpu3: cpu@3 {
85 clock-frequency = <0>;
86 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
87 d-cache-block-size = <64>;
88 d-cache-sets = <64>;
89 d-cache-size = <32768>;
90 d-tlb-sets = <1>;
91 d-tlb-size = <32>;
92 device_type = "cpu";
93 i-cache-block-size = <64>;
94 i-cache-sets = <64>;
95 i-cache-size = <32768>;
96 i-tlb-sets = <1>;
97 i-tlb-size = <32>;
98 mmu-type = "riscv,sv39";
99 reg = <3>;
100 riscv,isa = "rv64imafdc";
101 tlb-split;
102 cpu3_intc: interrupt-controller {
103 #interrupt-cells = <1>;
104 compatible = "riscv,cpu-intc";
105 interrupt-controller;
106 };
107 };
108 cpu4: cpu@4 {
109 clock-frequency = <0>;
110 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
111 d-cache-block-size = <64>;
112 d-cache-sets = <64>;
113 d-cache-size = <32768>;
114 d-tlb-sets = <1>;
115 d-tlb-size = <32>;
116 device_type = "cpu";
117 i-cache-block-size = <64>;
118 i-cache-sets = <64>;
119 i-cache-size = <32768>;
120 i-tlb-sets = <1>;
121 i-tlb-size = <32>;
122 mmu-type = "riscv,sv39";
123 reg = <4>;
124 riscv,isa = "rv64imafdc";
125 tlb-split;
126 cpu4_intc: interrupt-controller {
127 #interrupt-cells = <1>;
128 compatible = "riscv,cpu-intc";
129 interrupt-controller;
130 };
131 };
132 };
133 soc {
134 #address-cells = <2>;
135 #size-cells = <2>;
136 compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
137 ranges;
138 plic0: interrupt-controller@c000000 {
139 #interrupt-cells = <1>;
140 compatible = "sifive,plic-1.0.0";
141 reg = <0x0 0xc000000 0x0 0x4000000>;
142 riscv,ndev = <53>;
143 interrupt-controller;
144 interrupts-extended = <
145 &cpu0_intc 0xffffffff
146 &cpu1_intc 0xffffffff &cpu1_intc 9
147 &cpu2_intc 0xffffffff &cpu2_intc 9
148 &cpu3_intc 0xffffffff &cpu3_intc 9
149 &cpu4_intc 0xffffffff &cpu4_intc 9>;
150 };
151 prci: clock-controller@10000000 {
152 compatible = "sifive,fu540-c000-prci";
153 reg = <0x0 0x10000000 0x0 0x1000>;
154 clocks = <&hfclk>, <&rtcclk>;
155 #clock-cells = <1>;
156 };
157 uart0: serial@10010000 {
158 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
159 reg = <0x0 0x10010000 0x0 0x1000>;
160 interrupt-parent = <&plic0>;
161 interrupts = <4>;
162 clocks = <&prci 3>;
163 status = "disabled";
164 };
165 uart1: serial@10011000 {
166 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
167 reg = <0x0 0x10011000 0x0 0x1000>;
168 interrupt-parent = <&plic0>;
169 interrupts = <5>;
170 clocks = <&prci 3>;
171 status = "disabled";
172 };
173 i2c0: i2c@10030000 {
174 compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
175 reg = <0x0 0x10030000 0x0 0x1000>;
176 interrupt-parent = <&plic0>;
177 interrupts = <50>;
178 clocks = <&prci 3>;
179 reg-shift = <2>;
180 reg-io-width = <1>;
181 #address-cells = <1>;
182 #size-cells = <0>;
183 status = "disabled";
184 };
185 qspi0: spi@10040000 {
186 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
187 reg = <0x0 0x10040000 0x0 0x1000
188 0x0 0x20000000 0x0 0x10000000>;
189 interrupt-parent = <&plic0>;
190 interrupts = <51>;
191 clocks = <&prci 3>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194 status = "disabled";
195 };
196 qspi1: spi@10041000 {
197 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
198 reg = <0x0 0x10041000 0x0 0x1000
199 0x0 0x30000000 0x0 0x10000000>;
200 interrupt-parent = <&plic0>;
201 interrupts = <52>;
202 clocks = <&prci 3>;
203 #address-cells = <1>;
204 #size-cells = <0>;
205 status = "disabled";
206 };
207 qspi2: spi@10050000 {
208 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
209 reg = <0x0 0x10050000 0x0 0x1000>;
210 interrupt-parent = <&plic0>;
211 interrupts = <6>;
212 clocks = <&prci 3>;
213 #address-cells = <1>;
214 #size-cells = <0>;
215 status = "disabled";
216 };
217 eth0: ethernet@10090000 {
218 compatible = "sifive,fu540-c000-gem";
219 interrupt-parent = <&plic0>;
220 interrupts = <53>;
221 reg = <0x0 0x10090000 0x0 0x2000
222 0x0 0x100a0000 0x0 0x1000>;
223 local-mac-address = [00 00 00 00 00 00];
224 clock-names = "pclk", "hclk";
225 clocks = <&prci 2>, <&prci 2>;
226 #address-cells = <1>;
227 #size-cells = <0>;
228 status = "disabled";
229 };
231 };
232 };