src/mainboard/starlabs/starbook/variants/tgl/devtree.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <chip.h>
   4 #include <cpu/intel/turbo.h>
   5 #include <device/device.h>
   6 #include <device/pci_def.h>
   7 #include <option.h>
   8 #include <static.h>
   9 #include <types.h>
  10 #include <variants.h>
  11
  12 void devtree_update(void)
  13 {
  14         config_t *cfg = config_of_soc();
  15
  16         struct soc_power_limits_config *soc_conf_2core =
  17                 &cfg->power_limits_config[POWER_LIMITS_U_2_CORE];
  18
  19         struct soc_power_limits_config *soc_conf_4core =
  20                 &cfg->power_limits_config[POWER_LIMITS_U_4_CORE];
  21
  22         struct device *nic_dev = pcidev_on_root(0x14, 3);
  23         struct device *tbt_pci_dev = pcidev_on_root(0x07, 0);
  24         struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2);
  25         struct device *gna_dev = pcidev_on_root(0x08, 0);
  26
  27         uint8_t performance_scale = 100;
  28
  29         /* Set PL4 to 1.0C */
  30         soc_conf_2core->tdp_pl4                         = 65;
  31         soc_conf_4core->tdp_pl4                         = 65;
  32
  33         /* Set PL1 to 50% of PL2 */
  34         soc_conf_2core->tdp_pl1_override = (soc_conf_2core->tdp_pl2_override / 2) & ~1;
  35         soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl2_override / 2) & ~1;
  36
  37         /* Scale PL1 & PL2 based on CMOS settings */
  38         switch (get_power_profile(PP_POWER_SAVER)) {
  39         case PP_POWER_SAVER:
  40                 performance_scale                       -= 50;
  41                 cfg->tcc_offset                         = 30;
  42                 break;
  43         case PP_BALANCED:
  44                 performance_scale                       -= 25;
  45                 cfg->tcc_offset                         = 25;
  46                 break;
  47         case PP_PERFORMANCE:
  48                 /* Use the Intel defaults */
  49                 cfg->tcc_offset                         = 20;
  50                 break;
  51         }
  52
  53         soc_conf_2core->tdp_pl1_override = (soc_conf_2core->tdp_pl1_override * performance_scale) / 100;
  54         soc_conf_2core->tdp_pl2_override = (soc_conf_2core->tdp_pl2_override * performance_scale) / 100;
  55
  56         soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl1_override * performance_scale) / 100;
  57         soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100;
  58
  59         /* Enable/Disable Wireless based on CMOS settings */
  60         if (get_uint_option("wireless", 1) == 0)
  61                 nic_dev->enabled = 0;
  62
  63         /* Enable/Disable Webcam based on CMOS settings */
  64         cfg->usb2_ports[CONFIG_CCD_PORT].enable = get_uint_option("webcam", 1);
  65
  66         /* Enable/Disable Card Reader based on CMOS Settings */
  67         if (get_uint_option("card_reader", 1) == 0)
  68                 cfg->usb2_ports[5].enable = 0;
  69
  70         /* Enable/Disable Thunderbolt based on CMOS settings */
  71         if (get_uint_option("thunderbolt", 1) == 0) {
  72                 cfg->UsbTcPortEn = 0;
  73                 cfg->TcssXhciEn = 0;
  74                 tbt_pci_dev->enabled = 0;
  75                 tbt_dma_dev->enabled = 0;
  76         }
  77
  78         /* Enable/Disable GNA based on CMOS settings */
  79         if (get_uint_option("gna", 0) == 0)
  80                 gna_dev->enabled = 0;
  81 }