src/mainboard/system76/addw1/devicetree.cb

   1 # SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/intel/cannonlake
   4         register "common_soc_config" = "{
   5                 // Touchpad I2C bus
   6                 .i2c[0] = {
   7                         .speed = I2C_SPEED_FAST,
   8                         .rise_time_ns = 80,
   9                         .fall_time_ns = 110,
  10                 },
  11         }"
  12
  13 # CPU (soc/intel/cannonlake/cpu.c)
  14         # Power limit
  15         register "power_limits_config" = "{
  16                 .tdp_pl1_override = 45,
  17                 .tdp_pl2_override = 90,
  18         }"
  19
  20         # Enable Enhanced Intel SpeedStep
  21         register "eist_enable" = "true"
  22
  23 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
  24         register "enable_c6dram" = "1"
  25
  26 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
  27         # Misc
  28         register "AcousticNoiseMitigation" = "1"
  29
  30         # Power
  31         register "PchPmSlpS3MinAssert" = "3" # 50ms
  32         register "PchPmSlpS4MinAssert" = "1" # 1s
  33         register "PchPmSlpSusMinAssert" = "4" # 4s
  34         register "PchPmSlpAMinAssert" = "4" # 2s
  35
  36         # Thermal
  37         register "tcc_offset" = "8"
  38
  39         # Serial IRQ Continuous
  40         register "serirq_mode" = "SERIRQ_CONTINUOUS"
  41
  42 # PM Util (soc/intel/cannonlake/pmutil.c)
  43         # GPE configuration
  44         # Note that GPE events called out in ASL code rely on this
  45         # route. i.e. If this route changes then the affected GPE
  46         # offset bits also need to be changed.
  47         register "gpe0_dw0" = "PMC_GPP_K"
  48         register "gpe0_dw1" = "PMC_GPP_G"
  49         register "gpe0_dw2" = "PMC_GPP_E"
  50
  51 # Actual device tree
  52         device domain 0 on
  53                 subsystemid 0x1558 0x65d1 inherit
  54                 device ref peg0         on
  55                         # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
  56                         register "PcieClkSrcUsage[8]" = "0x40"
  57                         register "PcieClkSrcClkReq[8]" = "8"
  58                 end
  59                 device ref igpu         on      end
  60                 device ref dptf         on
  61                         register "Device4Enable" = "1"
  62                 end
  63                 device ref thermal      on      end
  64                 device ref xhci         on
  65                         register "usb2_ports" = "{
  66                                 [0] = USB2_PORT_TYPE_C(OC_SKIP),        /* USB 3.1 Gen 2 TYPE-C and DisplayPort */
  67                                 [1] = USB2_PORT_TYPE_C(OC_SKIP),        /* USB 3.1 Gen 2 TYPE-C */
  68                                 [2] = USB2_PORT_MID(OC_SKIP),           /* USB 3.1 Gen 2 */
  69                                 [4] = USB2_PORT_MID(OC_SKIP),           /* USB 3.1 Gen 1 audio */
  70                                 [5] = USB2_PORT_MID(OC_SKIP),           /* USB 3.1 Gen 1 back */
  71                                 [6] = USB2_PORT_MID(OC_SKIP),           /* Fingerprint */
  72                                 [7] = USB2_PORT_MID(OC_SKIP),           /* Per-Key RGB keyboard */
  73                                 [8] = USB2_PORT_MID(OC_SKIP),           /* Camera */
  74                                 [13] = USB2_PORT_MID(OC_SKIP),          /* Bluetooth */
  75                         }"
  76                         register "usb3_ports" = "{
  77                                 [0] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB 3.1 Gen 2 TYPE-C and DisplayPort */
  78                                 [1] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB 3.1 Gen 2 right */
  79                                 [2] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB 3.1 Gen 2 TYPE-C (without TBT) */
  80                                 [3] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB 3.1 Gen 2 TYPE-C (without TBT) */
  81                                 [4] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB 3.1 Gen 1 audio */
  82                                 [5] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB 3.1 Gen 1 back */
  83                         }"
  84                 end
  85                 device ref shared_sram  on      end
  86                 device ref cnvi_wifi    on
  87                         chip drivers/wifi/generic
  88                                 register "wake" = "PME_B0_EN_BIT"
  89                                 device generic 0 on end
  90                         end
  91                 end
  92                 device ref i2c0         on      end
  93                 device ref sata         on
  94                         register "SataPortsEnable" = "{
  95                                 [0] = 1, /* HDD (SATA0B) */
  96                                 [1] = 1, /* SSD1 (SATA1A) */
  97                         }"
  98                 end
  99                 device ref pcie_rp17    on
 100                         # PCI Express root port #17 x4, Clock 0 (Thunderbolt)
 101                         register "PcieRpEnable[16]" = "1"
 102                         register "PcieRpLtrEnable[16]" = "1"
 103                         register "PcieRpHotPlug[16]" = "1"
 104                         register "PcieClkSrcUsage[0]" = "16"
 105                         register "PcieClkSrcClkReq[0]" = "0"
 106                 end
 107                 device ref pcie_rp21    on
 108                         # PCI Express root port #21 x4, Clock 10 (SSD2)
 109                         register "PcieRpEnable[20]" = "1"
 110                         register "PcieRpLtrEnable[20]" = "1"
 111                         register "PcieClkSrcUsage[10]" = "20"
 112                         register "PcieClkSrcClkReq[10]" = "10"
 113                         register "PcieRpSlotImplemented[20]" = "1"
 114                 end
 115                 device ref pcie_rp9     on
 116                         # PCI Express root port #9 x4, Clock 9 (SSD1)
 117                         register "PcieRpEnable[8]" = "1"
 118                         register "PcieRpLtrEnable[8]" = "1"
 119                         register "PcieClkSrcUsage[9]" = "8"
 120                         register "PcieClkSrcClkReq[9]" = "9"
 121                         register "PcieRpSlotImplemented[8]" = "1"
 122                 end
 123                 device ref pcie_rp14    on
 124                         # PCI Express root port #14 x1, Clock 5 (GLAN)
 125                         register "PcieRpEnable[13]" = "1"
 126                         register "PcieRpLtrEnable[13]" = "1"
 127                         register "PcieClkSrcUsage[5]" = "13"
 128                         register "PcieClkSrcClkReq[5]" = "5"
 129                         register "PcieRpSlotImplemented[13]" = "1"
 130                 end
 131                 device ref pcie_rp15    on
 132                         # PCI Express root port #15 x1, Clock 7 (Card Reader)
 133                         register "PcieRpEnable[14]" = "1"
 134                         register "PcieRpLtrEnable[14]" = "1"
 135                         register "PcieClkSrcUsage[7]" = "14"
 136                         register "PcieClkSrcClkReq[7]" = "7"
 137                         register "PcieRpSlotImplemented[14]" = "1"
 138                 end
 139                 device ref pcie_rp16    on
 140                         # PCI Express root port #16 x1, Clock 6 (WLAN)
 141                         register "PcieRpEnable[15]" = "1"
 142                         register "PcieRpLtrEnable[15]" = "1"
 143                         register "PcieClkSrcUsage[6]" = "15"
 144                         register "PcieClkSrcClkReq[6]" = "6"
 145                         register "PcieRpSlotImplemented[15]" = "1"
 146                 end
 147                 device ref lpc_espi     on
 148                         register "gen1_dec" = "0x00040069"
 149                         register "gen2_dec" = "0x00fc0e01"
 150                         register "gen3_dec" = "0x00fc0f01"
 151                         chip drivers/pc80/tpm
 152                                 device pnp 0c31.0 on end
 153                         end
 154                 end
 155                 device ref hda          on
 156                         register "PchHdaAudioLinkHda" = "1"
 157                 end
 158                 device ref smbus        on
 159                         chip drivers/i2c/tas5825m
 160                                 register "id" = "0"
 161                                 device i2c 4e on end # (8bit address: 0x9c)
 162                         end
 163                 end
 164         end
 165 end