src/mainboard/system76/cml-u/variants/galp4/overridetree.cb

   1 # SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/intel/cannonlake
   4         device domain 0 on
   5                 subsystemid 0x1558 0x1403 inherit
   6
   7                 device ref xhci         on
   8                         register "usb2_ports" = "{
   9                                 [0] = USB2_PORT_MID(OC_SKIP),           /* Type-A port 1 */
  10                                 [1] = USB2_PORT_MID(OC_SKIP),           /* 3G / LTE */
  11                                 [2] = USB2_PORT_TYPE_C(OC_SKIP),        /* Type-C port 3 */
  12                                 [3] = USB2_PORT_MID(OC_SKIP),           /* USB Board port 4 */
  13                                 [6] = USB2_PORT_MAX(OC_SKIP),           /* Camera */
  14                                 [9] = USB2_PORT_MID(OC_SKIP),           /* Bluetooth */
  15                         }"
  16                         register "usb3_ports" = "{
  17                                 [0] = USB3_PORT_DEFAULT(OC_SKIP),       /* Type-A port 1 */
  18                                 [1] = USB3_PORT_DEFAULT(OC_SKIP),       /* 4G */
  19                                 [2] = USB3_PORT_DEFAULT(OC_SKIP),       /* Type-C port 3 */
  20                                 [3] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB Board port 4 */
  21                                 [4] = USB3_PORT_EMPTY,                  /* Used by TBT */
  22                                 [5] = USB3_PORT_EMPTY,                  /* Used by TBT */
  23                         }"
  24                 end
  25                 device ref i2c0         on
  26                         # I2C HID not supported on galp4
  27                 end
  28                 device ref sata         on
  29                         register "SataPortsEnable" = "{
  30                                 [0] = 1,
  31                                 [2] = 1,
  32                         }"
  33                 end
  34                 device ref pcie_rp5     on
  35                         # PCI Express Root port #5 x4, Clock 4 (TBT)
  36                         register "PcieRpEnable[4]" = "true"
  37                         register "PcieRpLtrEnable[4]" = "true"
  38                         register "PcieRpHotPlug[4]" = "1"
  39                         register "PcieClkSrcUsage[4]" = "4"
  40                         register "PcieClkSrcClkReq[4]" = "4"
  41                 end
  42                 device ref pcie_rp9     on
  43                         # PCI Express Root port #9 x1, Clock 3 (LAN)
  44                         register "PcieRpEnable[8]" = "true"
  45                         register "PcieRpLtrEnable[8]" = "true"
  46                         register "PcieClkSrcUsage[3]" = "8"
  47                         register "PcieClkSrcClkReq[3]" = "3"
  48                 end
  49                 device ref pcie_rp10    on
  50                         # PCI Express Root port #10 x1, Clock 2 (WLAN)
  51                         register "PcieRpEnable[9]" = "true"
  52                         register "PcieRpLtrEnable[9]" = "false"
  53                         register "PcieClkSrcUsage[2]" = "9"
  54                         register "PcieClkSrcClkReq[2]" = "2"
  55                 end
  56                 device ref pcie_rp13    on
  57                         # PCI Express Root port #13 x4, Clock 5 (NVMe)
  58                         register "PcieRpEnable[12]" = "true"
  59                         register "PcieRpLtrEnable[12]" = "true"
  60                         register "PcieClkSrcUsage[5]" = "12"
  61                         register "PcieClkSrcClkReq[5]" = "5"
  62                 end
  63                 device ref hda          on
  64                         register "PchHdaAudioLinkDmic0" = "1"
  65                         register "PchHdaAudioLinkDmic1" = "1"
  66                 end
  67         end
  68 end