src/mainboard/system76/rpl/variants/addw3/overridetree.cb

   1 # SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/intel/alderlake
   4         # Support 5600 MT/s memory
   5         register "max_dram_speed_mts" = "5600"
   6
   7         device domain 0 on
   8                 subsystemid 0x1558 0xa671 inherit
   9
  10                 #TODO: DDIB and DDID are both connected to TBT
  11
  12                 device ref xhci on
  13                         register "usb2_ports" = "{
  14                                 [0] = USB2_PORT_MID(OC_SKIP),           /* Type-A 3.2 Gen 1 (Left) */
  15                                 [1] = USB2_PORT_MID(OC_SKIP),           /* Type-A 2.0 (Left) */
  16                                 /* Port reset messaging cannot be used,
  17                                  * so do not use USB2_PORT_TYPE_C for these */
  18                                 [2] = USB2_PORT_MID(OC_SKIP),           /* Type-C 3.2 Gen 2 (Rear) */
  19                                 [8] = USB2_PORT_MID(OC_SKIP),           /* Type-C Thunderbolt (Right) */
  20                                 [10] = USB2_PORT_MID(OC_SKIP),          /* Camera */
  21                                 [11] = USB2_PORT_MID(OC_SKIP),          /* Secure Pad */
  22                                 [13] = USB2_PORT_MID(OC_SKIP),          /* Bluetooth */
  23                         }"
  24                         register "usb3_ports" = "{
  25                                 [0] = USB3_PORT_DEFAULT(OC_SKIP),       /* Type-A 3.2 Gen 1 (Left) */
  26                                 [2] = USB3_PORT_DEFAULT(OC_SKIP),       /* Type-C 3.2 Gen 2 (Rear) */
  27                         }"
  28                 end
  29
  30                 device ref i2c0 on
  31                         # Touchpad I2C bus
  32                         register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
  33                         chip drivers/i2c/hid
  34                                 register "generic.hid" = ""ELAN0412""
  35                                 register "generic.desc" = ""ELAN Touchpad""
  36                                 register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)"
  37                                 register "generic.detect" = "1"
  38                                 register "hid_desc_reg_offset" = "0x01"
  39                                 device i2c 15 on end
  40                         end
  41                         chip drivers/i2c/hid
  42                                 register "generic.hid" = ""FTCS1000""
  43                                 register "generic.desc" = ""FocalTech Touchpad""
  44                                 register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)"
  45                                 register "generic.detect" = "1"
  46                                 register "hid_desc_reg_offset" = "0x01"
  47                                 device i2c 38 on end
  48                         end
  49                 end
  50
  51                 device ref pcie5_0 on
  52                         # CPU PCIe RP#2 x8, Clock 14 (DGPU)
  53                         register "cpu_pcie_rp[CPU_RP(2)]" = "{
  54                                 .clk_src = 14,
  55                                 .clk_req = 14,
  56                                 .flags = PCIE_RP_LTR | PCIE_RP_AER,
  57                         }"
  58                 end
  59
  60                 device ref pcie_rp3 on
  61                         # PCH RP#3 x1, Clock 13 (GLAN)
  62                         # Clock source is shared with LAN and hence marked as free running.
  63                         register "pch_pcie_rp[PCH_RP(3)]" = "{
  64                                 .clk_src = 13,
  65                                 .clk_req = 13,
  66                                 .flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED,
  67                         }"
  68                         register "pcie_clk_config_flag[13]" = "PCIE_CLK_FREE_RUNNING"
  69                         device pci 00.0 on end
  70                 end
  71
  72                 device ref pcie_rp5 on
  73                         # PCH RP#5 x1, Clock 12 (CARD)
  74                         register "pch_pcie_rp[PCH_RP(5)]" = "{
  75                                 .clk_src = 12,
  76                                 .clk_req = 12,
  77                                 .flags = PCIE_RP_LTR | PCIE_RP_AER,
  78                         }"
  79                 end
  80
  81                 device ref pcie_rp8 on
  82                         # PCH RP#8 x1, Clock 11 (WLAN)
  83                         register "pch_pcie_rp[PCH_RP(8)]" = "{
  84                                 .clk_src = 11,
  85                                 .clk_req = 11,
  86                                 .flags = PCIE_RP_LTR | PCIE_RP_AER,
  87                         }"
  88                 end
  89
  90                 device ref pcie_rp13 on
  91                         # PCH RP#13 x4, Clock 10 (SSD1)
  92                         register "pch_pcie_rp[PCH_RP(13)]" = "{
  93                                 .clk_src = 10,
  94                                 .clk_req = 10,
  95                                 .flags = PCIE_RP_LTR | PCIE_RP_AER,
  96                         }"
  97                 end
  98
  99                 device ref pcie_rp21 on
 100                         # PCH RP#21 x4, Clock 15 (TBT)
 101                         register "pch_pcie_rp[PCH_RP(21)]" = "{
 102                                 .clk_src = 15,
 103                                 .clk_req = 15,
 104                                 .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR,
 105                         }"
 106                 end
 107
 108                 device ref pcie_rp25 on
 109                         # PCH RP#25 x4, Clock 8 (SSD2)
 110                         register "pch_pcie_rp[PCH_RP(25)]" = "{
 111                                 .clk_src = 8,
 112                                 .clk_req = 8,
 113                                 .flags = PCIE_RP_LTR | PCIE_RP_AER,
 114                         }"
 115                 end
 116
 117                 device ref gbe on end
 118         end
 119 end