src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb

   1 # SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/intel/tigerlake
   4         device domain 0 on
   5                 subsystemid 0x1558 0x50e1 inherit
   6
   7                 device ref peg1 on
   8                         # PCIe PEG1 x16, Clock 9 (DGPU)
   9                         register "PcieClkSrcUsage[9]" = "0x41"
  10                         register "PcieClkSrcClkReq[9]" = "9"
  11                         chip soc/intel/common/block/pcie/rtd3
  12                                 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
  13                                 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
  14                                 register "enable_delay_ms" = "16"
  15                                 register "enable_off_delay_ms" = "4"
  16                                 register "reset_delay_ms" = "10"
  17                                 register "reset_off_delay_ms" = "4"
  18                                 register "srcclk_pin" = "9" # PEG_CLKREQ#
  19                                 device generic 0 on end
  20                         end
  21                 end
  22                 device ref igpu on
  23                         # DDIB is HDMI
  24                         register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP"
  25                         register "DdiPortBHpd" = "1"
  26                         register "DdiPortBDdc" = "1"
  27                 end
  28                 device ref peg0 on
  29                         # PCIe PEG0 x4, Clock 7 (SSD1)
  30                         register "PcieClkSrcUsage[7]" = "0x40"
  31                         register "PcieClkSrcClkReq[7]" = "7"
  32                 end
  33                 device ref south_xhci on
  34                         register "usb2_ports" = "{
  35                                 [0] = USB2_PORT_MID(OC_SKIP),           /* USB 3.2 Gen 2 (Right) */
  36                                 [1] = USB2_PORT_MID(OC_SKIP),           /* USB 3.2 Gen 1 (Left) */
  37                                 [2] = USB2_PORT_TYPE_C(OC_SKIP),        /* USB 3.2 Gen 2 Type C (Back) */
  38                                 [5] = USB2_PORT_MID(OC_SKIP),           /* USB 2.0 (Left) */
  39                                 [7] = USB2_PORT_MID(OC_SKIP),           /* Camera */
  40                                 [8] = USB2_PORT_MID(OC_SKIP),           /* Per-Key */
  41                                 [9] = USB2_PORT_MID(OC_SKIP),           /* Fingerprint */
  42                                 [13] = USB2_PORT_MID(OC_SKIP),          /* Bluetooth */
  43                         }"
  44                         register "usb3_ports" = "{
  45                                 [0] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB 3.2 Gen 2 (Right) */
  46                                 [1] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB 3.2 Gen 1 (Left) */
  47                                 [2] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB 3.2 Gen 2 Type C (Back) */
  48                         }"
  49                 end
  50                 device ref sata on
  51                         register "SataPortsEnable" = "{
  52                                 [0] = 1, /* HDD (SATA0B) */
  53                                 [1] = 1, /* SSD2 (SATA1A) */
  54                         }"
  55                 end
  56                 device ref pcie_rp5 on
  57                         # PCIe root port #5 x1, Clock 8 (GLAN)
  58                         register "PcieRpLtrEnable[4]" = "1"
  59                         #register "PcieClkSrcUsage[8]" = "4"
  60                         register "PcieClkSrcClkReq[8]" = "8"
  61                 end
  62                 device ref pcie_rp7 on
  63                         # PCIe root port #7 x1, Clock 3 (CARD)
  64                         register "PcieRpLtrEnable[6]" = "1"
  65                         register "PcieClkSrcUsage[3]" = "6"
  66                         register "PcieClkSrcClkReq[3]" = "3"
  67                 end
  68                 device ref pcie_rp8 on
  69                         # PCIe root port #8 x1, Clock 2 (WLAN)
  70                         register "PcieRpLtrEnable[7]" = "1"
  71                         register "PcieClkSrcUsage[2]" = "7"
  72                         register "PcieClkSrcClkReq[2]" = "2"
  73                         register "PcieRpSlotImplemented[7]" = "1"
  74                 end
  75                 device ref pcie_rp9 on
  76                         # PCIe root port #9 x4, Clock 10 (SSD2)
  77                         register "PcieRpLtrEnable[8]" = "1"
  78                         register "PcieClkSrcUsage[10]" = "8"
  79                         register "PcieClkSrcClkReq[10]" = "10"
  80                         register "PcieRpSlotImplemented[8]" = "1"
  81                 end
  82                 device ref gbe on end
  83         end
  84 end