src/mainboard/system76/whl-u/devicetree.cb

   1 # SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/intel/cannonlake
   4         # Lock Down
   5         register "common_soc_config" = "{
   6                 .i2c[0] = {
   7                         .speed = I2C_SPEED_FAST,
   8                         .rise_time_ns = 80,
   9                         .fall_time_ns = 110,
  10                 },
  11         }"
  12
  13 # CPU (soc/intel/cannonlake/cpu.c)
  14         # Power limit
  15         register "power_limits_config" = "{
  16                 .tdp_pl1_override = 20,
  17                 .tdp_pl2_override = 30,
  18         }"
  19
  20         # Enable Enhanced Intel SpeedStep
  21         register "eist_enable" = "true"
  22
  23 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
  24         register "SaGv" = "SaGv_Enabled"
  25         register "enable_c6dram" = "1"
  26
  27 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
  28         # Serial I/O
  29         register "SerialIoDevMode" = "{
  30                 [PchSerialIoIndexI2C0] = PchSerialIoPci,
  31                 [PchSerialIoIndexUART2] = PchSerialIoPci,
  32         }"
  33
  34         # Misc
  35         register "AcousticNoiseMitigation" = "1"
  36
  37         # Power
  38         register "PchPmSlpS3MinAssert" = "3"    # 50ms
  39         register "PchPmSlpS4MinAssert" = "1"    # 1s
  40         register "PchPmSlpSusMinAssert" = "2"   # 500ms
  41         register "PchPmSlpAMinAssert" = "4"     # 2s
  42
  43         # Thermal
  44         register "tcc_offset" = "12"
  45
  46         # Serial IRQ Continuous
  47         register "serirq_mode" = "SERIRQ_CONTINUOUS"
  48
  49 # PM Util (soc/intel/cannonlake/pmutil.c)
  50         # GPE configuration
  51         # Note that GPE events called out in ASL code rely on this
  52         # route. i.e. If this route changes then the affected GPE
  53         # offset bits also need to be changed.
  54         register "gpe0_dw0" = "PMC_GPP_C"
  55         register "gpe0_dw1" = "PMC_GPP_D"
  56         register "gpe0_dw2" = "PMC_GPP_E"
  57
  58 # Actual device tree
  59         device domain 0 on
  60                 device ref igpu         on
  61                         register "gfx" = "GMA_STATIC_DISPLAYS(0)"
  62                 end
  63                 device ref dptf         on
  64                         register "Device4Enable" = "1"
  65                 end
  66                 device ref thermal      on  end
  67                 device ref xhci         on
  68                         register "usb2_ports" = "{
  69                                 [0] = USB2_PORT_MID(OC_SKIP),           /* USB-A */
  70                                 [1] = USB2_PORT_MID(OC_SKIP),           /* 3G / LTE */
  71                                 [2] = USB2_PORT_TYPE_C(OC_SKIP),        /* USB-C */
  72                                 [3] = USB2_PORT_MID(OC_SKIP),           /* USB-A */
  73                                 [6] = USB2_PORT_MAX(OC_SKIP),           /* Camera */
  74                                 [9] = USB2_PORT_MID(OC_SKIP),           /* Bluetooth */
  75                         }"
  76                         register "usb3_ports" = "{
  77                                 [0] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB-A */
  78                                 [1] = USB3_PORT_DEFAULT(OC_SKIP),       /* 4G on galp3-c, NC on darp5 */
  79                                 [2] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB-C */
  80                                 [3] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB-A */
  81                                 [4] = USB3_PORT_EMPTY,                  /* Used by TBT */
  82                                 [5] = USB3_PORT_EMPTY,                  /* Used by TBT */
  83                         }"
  84                 end
  85                 device ref cnvi_wifi    on
  86                         chip drivers/wifi/generic
  87                                 register "wake" = "PME_B0_EN_BIT"
  88                                 device generic 0 on end
  89                         end
  90                 end
  91                 device ref i2c0         on      end
  92                 device ref sata         on
  93                         register "SataPortsEnable" = "{
  94                                 [0] = 1,
  95                                 [2] = 1,
  96                         }"
  97                 end
  98                 device ref uart2        on      end
  99                 device ref pcie_rp1     on      end
 100                 device ref pcie_rp5     on
 101                         # PCI Express Root port #5 x4, Clock 4 (TBT)
 102                         register "PcieRpEnable[4]" = "1"
 103                         register "PcieRpLtrEnable[4]" = "1"
 104                         register "PcieRpHotPlug[4]" = "1"
 105                         register "PcieClkSrcUsage[4]" = "4"
 106                         register "PcieClkSrcClkReq[4]" = "4"
 107                 end
 108                 device ref pcie_rp9     on
 109                         # PCI Express Root port #9 x1, Clock 3 (LAN)
 110                         register "PcieRpEnable[8]" = "1"
 111                         register "PcieRpLtrEnable[8]" = "1"
 112                         register "PcieClkSrcUsage[3]" = "8"
 113                         register "PcieClkSrcClkReq[3]" = "3"
 114                 end
 115                 device ref pcie_rp10    on
 116                         # PCI Express Root port #10 x1, Clock 2 (WLAN)
 117                         register "PcieRpEnable[9]" = "1"
 118                         register "PcieRpLtrEnable[9]" = "0"
 119                         register "PcieClkSrcUsage[2]" = "9"
 120                         register "PcieClkSrcClkReq[2]" = "2"
 121                 end
 122                 device ref pcie_rp13    on
 123                         # PCI Express Root port #13 x4, Clock 5 (NVMe)
 124                         register "PcieRpEnable[12]" = "1"
 125                         register "PcieRpLtrEnable[12]" = "1"
 126                         register "PcieClkSrcUsage[5]" = "12"
 127                         register "PcieClkSrcClkReq[5]" = "5"
 128                 end
 129                 device ref lpc_espi     on
 130                         register "gen1_dec" = "0x000c0081"
 131                         register "gen2_dec" = "0x00040069"
 132                         register "gen3_dec" = "0x00fc0e01"
 133                         register "gen4_dec" = "0x00fc0f01"
 134                         chip drivers/pc80/tpm
 135                                 device pnp 0c31.0 on end
 136                         end
 137                 end
 138                 device ref hda          on
 139                         register "PchHdaAudioLinkHda" = "1"
 140                         register "PchHdaAudioLinkDmic0" = "1"
 141                         register "PchHdaAudioLinkDmic1" = "1"
 142                 end
 143                 device ref smbus        on      end
 144         end
 145 end