commonlib: Refactor CSE sync eventLog
[coreboot2.git] / src / northbridge / amd / pi / 00730F01 / chipset.cb
blobc03882cc61257465a4dc374336e92f82da3de0af
1 # SPDX-License-Identifier: GPL-2.0-only
3 chip northbridge/amd/pi/00730F01
4 device cpu_cluster 0 on
5 ops amd_fam16_mod30_cpu_bus_ops
6 end
8 device domain 0 on
9 ops amd_fam16_mod30_pci_domain_ops
10 device pci 0.0 alias gnb on
11 ops amd_pi_northbridge_ops
12 end
13 device pci 0.2 alias iommu off
14 ops amd_pi_iommu_ops
15 end
16 device pci 1.0 alias gfx off end
17 device pci 1.1 alias gfx_hda off end
18 device pci 2.0 on end # Dummy device function, do not disable
19 device pci 2.1 alias gpp_bridge_0 off end
20 device pci 2.2 alias gpp_bridge_1 off end
21 device pci 2.3 alias gpp_bridge_2 off end
22 device pci 2.4 alias gpp_bridge_3 off end
23 device pci 2.5 alias gpp_bridge_4 off end
24 device pci 8.0 alias psp on end
26 chip southbridge/amd/pi/hudson
27 device pci 10.0 alias xhci off end
28 device pci 11.0 alias sata off end
29 device pci 12.0 alias ehci_0 off end
30 device pci 13.0 alias ehci_1 off end
31 device pci 14.0 alias smbus on end
32 device pci 14.2 alias hda off end
33 device pci 14.3 alias lpc_bridge on end
34 device pci 14.7 alias sdhci off end
35 device pci 16.0 alias ehci_2 off end
36 end
38 device pci 18.0 alias ht_0 on end
39 device pci 18.1 alias ht_1 on end
40 device pci 18.2 alias ht_2 on end
41 device pci 18.3 alias ht_3 on end
42 device pci 18.4 alias ht_4 on end
43 device pci 18.5 alias ht_5 on end
44 end
45 end