src/northbridge/intel/gm45/iommu.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <stdint.h>
   4
   5 #include <device/pci_ops.h>
   6 #include <device/pci_def.h>
   7
   8 #include "gm45.h"
   9
  10 void init_iommu(void)
  11 {
  12         /* FIXME: proper test? */
  13         int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff;
  14         int stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION);
  15
  16         mchbar_write32(0x28, IOMMU_BASE1 | 1); /* HDA @ 0:1b.0 */
  17         if (stepping != STEPPING_B2) {
  18                 /* The official workaround is to run SMM every 64ms.
  19                    The only winning move is not to play. */
  20                 mchbar_write32(0x18, IOMMU_BASE2 | 1); /* IGD @ 0:2.0-1 */
  21         } else {
  22                 /* write-once, so lock it down */
  23                 mchbar_write32(0x18, 0); /* disable IOMMU for IGD @ 0:2.0-1 */
  24         }
  25         if (me_active) {
  26                 mchbar_write32(0x10, IOMMU_BASE3 | 1); /* ME  @ 0:3.0-3 */
  27         } else {
  28                 mchbar_write32(0x10, 0); /* disable IOMMU for ME */
  29         }
  30         mchbar_write32(0x20, IOMMU_BASE4 | 1); /* all other DMA sources */
  31
  32         if (stepping == STEPPING_B3) {
  33                 mchbar_setbits8(0xffc, 1 << 4);
  34                 const pci_devfn_t peg = PCI_DEV(0, 1, 0);
  35
  36                 /* FIXME: proper test? */
  37                 if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff)
  38                         pci_or_config32(peg, 0xfc, 1 << 15);
  39         }
  40
  41         /* final */
  42         mchbar_setbits8(0x94, 1 << 3);
  43 }