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cbfs: Remove remnants of ext-win-*
[coreboot2.git] / src / northbridge / intel / haswell / broadwell_mrc / raminit.c
blobbeae4965ffd6d5cf08107e0f5e1846600aa2540a
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <assert.h>
4 #include <console/console.h>
5 #include <console/streams.h>
6 #include <console/usb.h>
7 #include <string.h>
8 #include <cbmem.h>
9 #include <cbfs.h>
10 #include <cf9_reset.h>
11 #include <device/dram/ddr3.h>
12 #include <memory_info.h>
13 #include <mrc_cache.h>
14 #include <device/device.h>
15 #include <device/pci_def.h>
16 #include <device/pci_ops.h>
17 #include <device/dram/ddr3.h>
18 #include <northbridge/intel/haswell/chip.h>
19 #include <northbridge/intel/haswell/haswell.h>
20 #include <northbridge/intel/haswell/raminit.h>
21 #include <smbios.h>
22 #include <spd.h>
23 #include <static.h>
24 #include <security/vboot/vboot_common.h>
25 #include <commonlib/region.h>
26 #include <southbridge/intel/lynxpoint/me.h>
27 #include <southbridge/intel/lynxpoint/pch.h>
28 #include <timestamp.h>
29 #include <types.h>
30
31 #include "pei_data.h"
32
33 static void save_mrc_data(struct pei_data *pei_data)
34 {
35 printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save,
36 pei_data->data_to_save_size);
37
38 if (pei_data->data_to_save != NULL && pei_data->data_to_save_size > 0)
39 mrc_cache_stash_data(MRC_TRAINING_DATA, 0,
40 pei_data->data_to_save,
41 pei_data->data_to_save_size);
42 }
43
44 static const char *const ecc_decoder[] = {
45 "inactive",
46 "active on IO",
47 "disabled on IO",
48 "active",
49 };
50
51 /*
52 * Dump in the log memory controller configuration as read from the memory
53 * controller registers.
54 */
55 static void report_memory_config(void)
56 {
57 int i;
58
59 const u32 addr_decoder_common = mchbar_read32(MAD_CHNL);
60
61 printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
62 (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
63
64 printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
65 (addr_decoder_common >> 0) & 3,
66 (addr_decoder_common >> 2) & 3,
67 (addr_decoder_common >> 4) & 3);
68
69 for (i = 0; i < NUM_CHANNELS; i++) {
70 const u32 ch_conf = mchbar_read32(MAD_DIMM(i));
71
72 printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
73 printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
74 printk(BIOS_DEBUG, " enhanced interleave mode %s\n",
75 ((ch_conf >> 22) & 1) ? "on" : "off");
76
77 printk(BIOS_DEBUG, " rank interleave %s\n",
78 ((ch_conf >> 21) & 1) ? "on" : "off");
79
80 printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n",
81 ((ch_conf >> 0) & 0xff) * 256,
82 ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
83 ((ch_conf >> 17) & 1) ? "dual" : "single",
84 ((ch_conf >> 16) & 1) ? "" : ", selected");
85
86 printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n",
87 ((ch_conf >> 8) & 0xff) * 256,
88 ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32",
89 ((ch_conf >> 18) & 1) ? "dual" : "single",
90 ((ch_conf >> 16) & 1) ? ", selected" : "");
91 }
92 }
93
94 typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data);
95
96 static void ABI_X86 send_to_console(unsigned char b)
97 {
98 console_tx_byte(b);
99 }
100
101 /*
102 * Find PEI executable in coreboot filesystem and execute it.
103 */
104 static void sdram_initialize(struct pei_data *pei_data)
105 {
106 size_t mrc_size;
107 pei_wrapper_entry_t entry;
108 int ret;
109
110 /* Assume boot device is memory mapped. */
111 assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
112
113 pei_data->saved_data =
114 mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0,
115 &mrc_size);
116 if (pei_data->saved_data) {
117 /* MRC cache found */
118 pei_data->saved_data_size = mrc_size;
119 } else if (pei_data->boot_mode == ACPI_S3) {
120 /* Waking from S3 and no cache. */
121 printk(BIOS_DEBUG,
122 "No MRC cache found in S3 resume path.\n");
123 post_code(POSTCODE_RESUME_FAILURE);
124 system_reset();
125 } else {
126 printk(BIOS_DEBUG, "No MRC cache found.\n");
127 }
128
129 /*
130 * Do not use saved pei data. Can be set by mainboard romstage
131 * to force a full train of memory on every boot.
132 */
133 if (pei_data->disable_saved_data) {
134 printk(BIOS_DEBUG, "Disabling PEI saved data by request\n");
135 pei_data->saved_data = NULL;
136 pei_data->saved_data_size = 0;
137 }
138
139 /* We don't care about leaking the mapping */
140 entry = cbfs_ro_map("mrc.bin", NULL);
141 if (entry == NULL)
142 die("mrc.bin not found!");
143
144 printk(BIOS_DEBUG, "Starting Memory Reference Code\n");
145
146 ret = entry(pei_data);
147 if (ret < 0)
148 die("pei_data version mismatch\n");
149
150 /* Print the MRC version after executing the UEFI PEI stage. */
151 u32 version = mchbar_read32(MRC_REVISION);
152 printk(BIOS_DEBUG, "MRC Version %u.%u.%u Build %u\n",
153 (version >> 24) & 0xff, (version >> 16) & 0xff,
154 (version >> 8) & 0xff, (version >> 0) & 0xff);
155
156 report_memory_config();
157 }
158
159 static uint8_t nb_get_ecc_type(const uint32_t capid0_a)
160 {
161 return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT;
162 }
163
164 static uint16_t nb_slots_per_channel(const uint32_t capid0_a)
165 {
166 return !(capid0_a & CAPID_DDPCD) + 1;
167 }
168
169 static uint16_t nb_number_of_channels(const uint32_t capid0_a)
170 {
171 return !(capid0_a & CAPID_PDCD) + 1;
172 }
173
174 static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a)
175 {
176 uint32_t ddrsz;
177
178 /* Values from documentation, which assume two DIMMs per channel */
179 switch (CAPID_DDRSZ(capid0_a)) {
180 case 1:
181 ddrsz = 8192;
182 break;
183 case 2:
184 ddrsz = 2048;
185 break;
186 case 3:
187 ddrsz = 512;
188 break;
189 default:
190 ddrsz = 16384;
191 break;
192 }
193
194 /* Account for the maximum number of DIMMs per channel */
195 return (ddrsz / 2) * nb_slots_per_channel(capid0_a);
196 }
197
198 static void setup_sdram_meminfo(struct pei_data *pei_data)
199 {
200 unsigned int dimm_cnt = 0;
201
202 struct memory_info *mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
203 if (!mem_info)
204 die("Failed to add memory info to CBMEM.\n");
205
206 memset(mem_info, 0, sizeof(struct memory_info));
207
208 const u32 ddr_frequency = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100;
209
210 for (unsigned int ch = 0; ch < NUM_CHANNELS; ch++) {
211 const u32 ch_conf = mchbar_read32(MAD_DIMM(ch));
212 for (unsigned int slot = 0; slot < NUM_SLOTS; slot++) {
213 const u32 dimm_size = ((ch_conf >> (slot * 8)) & 0xff) * 256;
214 if (dimm_size) {
215 struct dimm_info *dimm = &mem_info->dimm[dimm_cnt];
216 dimm->dimm_size = dimm_size;
217 dimm->ddr_type = MEMORY_TYPE_DDR3;
218 dimm->ddr_frequency = ddr_frequency;
219 dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + slot)) & 1);
220 dimm->channel_num = ch;
221 dimm->dimm_num = slot;
222 dimm->bank_locator = ch * 2;
223 memcpy(dimm->serial,
224 &pei_data->spd_data[ch][slot][SPD_DDR3_SERIAL_NUM],
225 SPD_DDR3_SERIAL_LEN);
226 memcpy(dimm->module_part_number,
227 &pei_data->spd_data[ch][slot][SPD_DDR3_PART_NUM],
228 SPD_DDR3_PART_LEN);
229 dimm->mod_id =
230 (pei_data->spd_data[ch][slot][SPD_DDR3_MOD_ID2] << 8) |
231 (pei_data->spd_data[ch][slot][SPD_DDR3_MOD_ID1] & 0xff);
232 dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM;
233 dimm->bus_width = MEMORY_BUS_WIDTH_64;
234 dimm_cnt++;
235 }
236 }
237 }
238 mem_info->dimm_cnt = dimm_cnt;
239
240 const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
241
242 const uint16_t channels = nb_number_of_channels(capid0_a);
243
244 mem_info->ecc_type = nb_get_ecc_type(capid0_a);
245 mem_info->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a);
246 mem_info->number_of_devices = channels * nb_slots_per_channel(capid0_a);
247 }
248
249 #include <device/smbus_host.h>
250
251 /* Copy SPD data for on-board memory */
252 static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi)
253 {
254 if (!CONFIG(HAVE_SPD_IN_CBFS))
255 return;
256
257 printk(BIOS_DEBUG, "SPD index %d\n", spdi->spd_index);
258
259 size_t spd_file_len;
260 uint8_t *spd_file = cbfs_map("spd.bin", &spd_file_len);
261
262 if (!spd_file)
263 die("SPD data not found.");
264
265 if (spd_file_len < ((spdi->spd_index + 1) * SPD_SIZE_MAX_DDR3)) {
266 printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
267 spdi->spd_index = 0;
268 }
269
270 if (spd_file_len < SPD_SIZE_MAX_DDR3)
271 die("Missing SPD data.");
272
273 /* MRC only uses index 0, but coreboot uses the other indices */
274 memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_SIZE_MAX_DDR3),
275 SPD_SIZE_MAX_DDR3);
276
277 for (size_t i = 1; i < ARRAY_SIZE(spdi->addresses); i++) {
278 if (spdi->addresses[i] == SPD_MEMORY_DOWN)
279 memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_SIZE_MAX_DDR3);
280 }
281 }
282
283 /*
284 * 0 = leave channel enabled
285 * 1 = disable dimm 0 on channel
286 * 2 = disable dimm 1 on channel
287 * 3 = disable dimm 0+1 on channel
288 */
289 static int make_channel_disabled_mask(const struct pei_data *pd, int ch)
290 {
291 return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1);
292 }
293
294 static enum pei_usb2_port_location map_to_pei_usb2_location(const enum usb2_port_location loc)
295 {
296 /* TODO: USB_PORT_NGFF_DEVICE_DOWN (not used by any board, though) */
297 static const enum pei_usb2_port_location map[] = {
298 [USB_PORT_SKIP] = PEI_USB_PORT_SKIP,
299 [USB_PORT_BACK_PANEL] = PEI_USB_PORT_BACK_PANEL,
300 [USB_PORT_FRONT_PANEL] = PEI_USB_PORT_FRONT_PANEL,
301 [USB_PORT_DOCK] = PEI_USB_PORT_DOCK,
302 [USB_PORT_MINI_PCIE] = PEI_USB_PORT_MINI_PCIE,
303 [USB_PORT_FLEX] = PEI_USB_PORT_FLEX,
304 [USB_PORT_INTERNAL] = PEI_USB_PORT_INTERNAL,
305 };
306 return loc >= ARRAY_SIZE(map) ? PEI_USB_PORT_SKIP : map[loc];
307 }
308
309 static uint8_t map_to_pei_oc_pin(const uint8_t oc_pin)
310 {
311 return oc_pin >= USB_OC_PIN_SKIP ? PEI_USB_OC_PIN_SKIP : oc_pin;
312 }
313
314 static bool early_init_native(int s3resume)
315 {
316 printk(BIOS_DEBUG, "Starting native platform initialisation\n");
317
318 intel_early_me_init();
319 /** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
320 const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
321
322 early_pch_init_native(s3resume);
323
324 if (!CONFIG(INTEL_LYNXPOINT_LP))
325 dmi_early_init();
326
327 return cpu_replaced;
328 }
329
330 void perform_raminit(const int s3resume)
331 {
332 const struct northbridge_intel_haswell_config *cfg = config_of_soc();
333
334 struct pei_data pei_data = {
335 .pei_version = PEI_VERSION,
336 .board_type = (enum board_type)get_pch_platform_type(),
337 .usbdebug = CONFIG(USBDEBUG),
338 .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
339 .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
340 .ehcibar = CONFIG_EHCI_BAR,
341 .xhcibar = 0xd7000000,
342 .gttbar = 0xe0000000,
343 .pmbase = DEFAULT_PMBASE,
344 .gpiobase = DEFAULT_GPIOBASE,
345 .tseg_size = CONFIG_SMM_TSEG_SIZE,
346 .temp_mmio_base = 0xfed08000,
347 .ec_present = cfg->ec_present,
348 .dq_pins_interleaved = cfg->dq_pins_interleaved,
349 .tx_byte = send_to_console,
350 .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH),
351 .rcba = CONFIG_FIXED_RCBA_MMIO_BASE, /* Might be unused */
352 };
353
354 for (size_t i = 0; i < ARRAY_SIZE(mainboard_usb2_ports); i++) {
355 /* If a port is not enabled, skip it */
356 if (!mainboard_usb2_ports[i].enable) {
357 pei_data.usb2_ports[i].oc_pin = PEI_USB_OC_PIN_SKIP;
358 pei_data.usb2_ports[i].location = PEI_USB_PORT_SKIP;
359 continue;
360 }
361 const enum usb2_port_location loc = mainboard_usb2_ports[i].location;
362 const uint8_t oc_pin = mainboard_usb2_ports[i].oc_pin;
363 pei_data.usb2_ports[i].length = mainboard_usb2_ports[i].length;
364 pei_data.usb2_ports[i].enable = mainboard_usb2_ports[i].enable;
365 pei_data.usb2_ports[i].oc_pin = map_to_pei_oc_pin(oc_pin);
366 pei_data.usb2_ports[i].location = map_to_pei_usb2_location(loc);
367 }
368
369 for (size_t i = 0; i < ARRAY_SIZE(mainboard_usb3_ports); i++) {
370 const uint8_t oc_pin = mainboard_usb3_ports[i].oc_pin;
371 pei_data.usb3_ports[i].enable = mainboard_usb3_ports[i].enable;
372 pei_data.usb3_ports[i].oc_pin = map_to_pei_oc_pin(oc_pin);
373 }
374
375 /* Broadwell MRC uses ACPI values for boot_mode */
376 pei_data.boot_mode = s3resume ? ACPI_S3 : ACPI_S0;
377
378 struct spd_info spdi = {0};
379 get_spd_info(&spdi, cfg);
380
381 /*
382 * Read the SPDs over SMBus in coreboot code so that the data can be used to
383 * populate meminfo. MRC returns some data, but it seems to be incomplete.
384 */
385 for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++) {
386 const uint8_t addr = spdi.addresses[i];
387 pei_data.spd_addresses[i] = addr == SPD_MEMORY_DOWN ? 0xff : addr << 1;
388 if (addr == SPD_MEMORY_DOWN)
389 continue;
390
391 if (i2c_eeprom_read(addr, 0, 256, pei_data.spd_data[i / 2][i % 2]) != 256) {
392 printk(BIOS_ERR, "0x%02x failed to read\n", addr);
393 memset(pei_data.spd_data[i / 2][i % 2], 0, 256);
394 }
395 }
396
397 /* Calculate unimplemented DIMM slots for each channel */
398 pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0);
399 pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1);
400
401 for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++)
402 pei_data.spd_addresses[i] = 0;
403
404 if (early_init_native(s3resume))
405 pei_data.disable_saved_data = true;
406
407 timestamp_add_now(TS_INITRAM_START);
408
409 copy_spd(&pei_data, &spdi);
410
411 sdram_initialize(&pei_data);
412
413 timestamp_add_now(TS_INITRAM_END);
414
415 if (intel_early_me_uma_size() > 0) {
416 /*
417 * The 'other' success value is to report loss of memory
418 * consistency to ME if warm boot was downgraded to cold.
419 * However, we can't tell if MRC downgraded the bootmode.
420 */
421 intel_early_me_init_done(ME_INIT_STATUS_SUCCESS_OTHER);
422 }
423
424 intel_early_me_status();
425
426 int cbmem_was_initted = !cbmem_recovery(s3resume);
427 if (s3resume && !cbmem_was_initted) {
428 /* Failed S3 resume, reset to come up cleanly */
429 printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");
430 system_reset();
431 }
432
433 /* Save data returned from MRC on non-S3 resumes. */
434 if (!s3resume)
435 save_mrc_data(&pei_data);
436
437 setup_sdram_meminfo(&pei_data);
438 }
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